[gcc r13-4105] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori

[gcc r13-4105] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori

[Philipp Tomsich]

https://gcc.gnu.org/g:ac74b3f82b339569b34dc9d1330c2faf74a1c82a

commit r13-4105-gac74b3f82b339569b34dc9d1330c2faf74a1c82a
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Thu May 12 15:11:20 2022 +0200

    RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
    
    We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
    by splitting it into a zero-extraction (bext) and an xori.  This both
    avoids burning a register on a temporary and generates a sequence that
    clearly captures 'extract bit, then invert bit'.
    
    This change improves the previously generated
        srl   a0,a0,a1
        not   a0,a0
        andi  a0,a0,1
    into
        bext  a0,a0,a1
        xori  a0,a0,1
    
    Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
    
    gcc/ChangeLog:
    
            * config/riscv/bitmanip.md: Add split covering
            "(a & (1 << BIT_NO)) ? 0 : 1".
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/zbs-bext.c: Add testcases.
            * gcc.target/riscv/zbs-bexti.c: Add testcases.

Diff:
---
 gcc/config/riscv/bitmanip.md               | 15 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/zbs-bext.c  | 10 ++++++++--
 gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 10 ++++++++--
 3 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 86cc85001c3..fb062f6eb43 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -414,3 +414,18 @@
   "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
   "bexti\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
+
+;; Split for "(a & (1 << BIT_NO)) ? 0 : 1":
+;; We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1",
+;; so we don't have to use a temporary.  Instead we extract the bit and then
+;; invert bit 0 ("a ^ 1") only.
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+	(and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
+				  (subreg:QI (match_operand:X 2 "register_operand") 0)))
+	       (const_int 1)))]
+  "TARGET_ZBS"
+  [(set (match_dup 0) (zero_extract:X (match_dup 1)
+				      (const_int 1)
+				      (match_dup 2)))
+   (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index 8de9c5a167c..a8aadb60390 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -23,16 +23,22 @@ long bext64_1(long a, char bitno)
 
 long bext64_2(long a, char bitno)
 {
-  return (a & (1UL << bitno)) ? 0 : -1;
+  return (a & (1UL << bitno)) ? 0 : 1;
 }
 
 long bext64_3(long a, char bitno)
+{
+  return (a & (1UL << bitno)) ? 0 : -1;
+}
+
+long bext64_4(long a, char bitno)
 {
   return (a & (1UL << bitno)) ? -1 : 0;
 }
 
 /* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-/* { dg-final { scan-assembler-times "bext\t" 4 } } */
+/* { dg-final { scan-assembler-times "bext\t" 5 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
 /* { dg-final { scan-assembler-times "addi\t" 1 } } */
 /* { dg-final { scan-assembler-times "neg\t" 1 } } */
 /* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
index 30b69c9bc3e..c15098eb6cc 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
@@ -12,14 +12,20 @@ long bexti64_1(long a, char bitno)
 
 long bexti64_2(long a, char bitno)
 {
-  return (a & (1UL << BIT_NO)) ? 0 : -1;
+  return (a & (1UL << BIT_NO)) ? 0 : 1;
 }
 
 long bexti64_3(long a, char bitno)
+{
+  return (a & (1UL << BIT_NO)) ? 0 : -1;
+}
+
+long bexti64_4(long a, char bitno)
 {
   return (a & (1UL << BIT_NO)) ? -1 : 0;
 }
 
-/* { dg-final { scan-assembler-times "bexti\t" 3 } } */
+/* { dg-final { scan-assembler-times "bexti\t" 4 } } */
+/* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */
 /* { dg-final { scan-assembler-times "addi\t" 1 } } */
 /* { dg-final { scan-assembler-times "neg\t" 1 } } */