[gcc(refs/users/aoliva/heads/testme)] [PR40457] [arm] expand SI-aligned movdi into pair of movsi

[Alexandre Oliva <aoliva@gcc.gnu.org>]

https://gcc.gnu.org/g:cec475ae63c3659241dbd5c474990b5103148f86

commit cec475ae63c3659241dbd5c474990b5103148f86
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Thu Dec 1 04:38:48 2022 -0300

    [PR40457] [arm] expand SI-aligned movdi into pair of movsi
    
    When expanding a misaligned DImode move, emit aligned SImode moves if
    the parts are sufficiently aligned.  This enables neighboring stores
    to be peephole-combined into stm, as expected by the PR40457 testcase,
    even after SLP vectorizes the originally aligned SImode stores into a
    misaligned DImode store.
    
    
    for  gcc/ChangeLog
    
            PR target/40457
            * config/arm/arm.md (movmisaligndi): Prefer aligned SImode
            moves.
    
    
    Change-Id: Ib91440e12e6ff424e3e7359874bf38c2779887a0
    TN: VB12-014

Diff:
---
 gcc/config/arm/arm.md | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 69bf343fb0e..a9eb0299aa7 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12783,8 +12783,16 @@
   rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]);
   rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]);
 
-  emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
-  emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+  if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode))
+    {
+      emit_move_insn (lo_op0, lo_op1);
+      emit_move_insn (hi_op0, hi_op1);
+    }
+  else
+    {
+      emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
+      emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+    }
   DONE;
 })