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From: Alexandre Oliva <aoliva@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [PR40457] [arm] expand SI-aligned movdi into pair of movsi Date: Sat, 3 Dec 2022 07:33:09 +0000 (GMT) [thread overview] Message-ID: <20221203073309.090913858434@sourceware.org> (raw) https://gcc.gnu.org/g:ff44d83e0f3577412a333b2c4a82cf1806bdf3f9 commit ff44d83e0f3577412a333b2c4a82cf1806bdf3f9 Author: Alexandre Oliva <oliva@adacore.com> Date: Fri Dec 2 03:28:06 2022 -0300 [PR40457] [arm] expand SI-aligned movdi into pair of movsi When expanding a misaligned DImode move, emit aligned SImode moves if the parts are sufficiently aligned. This enables neighboring stores to be peephole-combined into stm, as expected by the PR40457 testcase, even after SLP vectorizes the originally aligned SImode stores into a misaligned DImode store. for gcc/ChangeLog PR target/40457 * config/arm/arm.md (movmisaligndi): Prefer aligned SImode moves. Diff: --- gcc/config/arm/arm.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 69bf343fb0e..a9eb0299aa7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12783,8 +12783,16 @@ rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); - emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); - emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode)) + { + emit_move_insn (lo_op0, lo_op1); + emit_move_insn (hi_op0, hi_op1); + } + else + { + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + } DONE; })
next reply other threads:[~2022-12-03 7:33 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-03 7:33 Alexandre Oliva [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-12-01 7:40 Alexandre Oliva
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