[gcc/vrull/heads/for-upstream] (18 commits) Add new flag 'falign-arrays'

[gcc/vrull/heads/for-upstream] (18 commits) Add new flag 'falign-arrays'

[Philipp Tomsich]

The branch 'vrull/heads/for-upstream' was updated to point to:

 85b75e273cf... Add new flag 'falign-arrays'

It previously pointed to:

 19954801e11... Add new flag 'falign-arrays'

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------

  1995480... Add new flag 'falign-arrays'
  c4548b8... riscv: Add support for str(n)cmp inline expansion
  3e7bc4c... riscv: Add support for strlen inline expansion
  c58e424... riscv: Use by-pieces to do overlapping accesses in block_mo
  db2e8c8... riscv: Move riscv_block_move_loop to separate file
  72b806c... riscv: Enable overlap-by-pieces via tune param
  d7378ac... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  f4fca6a... RISC-V: Use .p2align for code-alignment
  09787e9... ifcvt: add if-conversion to conditional-zero instructions
  e4d96fa... RISC-V: Ventana-VT1 supports XVentanaCondOps
  71b468d... RISC-V: Support immediates in XVentanaCondOps
  7a87a85... RISC-V: Add instruction fusion (for ventana-vt1)
  9d95637... RISC-V: Add basic support for the Ventana-VT1 core
  95e8d5d... RISC-V: Recognize bexti in negated if-conversion
  95fbae4... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  852dc40... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
  01d2399... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if
  d7568da... RISC-V: Recognize xventanacondops extension


Summary of changes (added commits):
-----------------------------------

  85b75e2... Add new flag 'falign-arrays'
  64014fe... riscv: Add support for str(n)cmp inline expansion
  630b7f6... riscv: Add support for strlen inline expansion
  69da0a0... riscv: Use by-pieces to do overlapping accesses in block_mo
  caf45ba... riscv: Move riscv_block_move_loop to separate file
  bf45c8e... riscv: Enable overlap-by-pieces via tune param
  de66611... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  c16304a... RISC-V: Use .p2align for code-alignment
  02055c4... ifcvt: add if-conversion to conditional-zero instructions
  bfb9bc3... RISC-V: Ventana-VT1 supports XVentanaCondOps
  1b99fc3... RISC-V: Support immediates in XVentanaCondOps
  07d79c2... RISC-V: Add instruction fusion (for ventana-vt1)
  13b2130... RISC-V: Add basic support for the Ventana-VT1 core
  b927329... RISC-V: Recognize bexti in negated if-conversion
  029a73a... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  b6a9dbe... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
  efee69b... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if
  7684dea... RISC-V: Recognize xventanacondops extension