[gcc r13-4680] AArch64: Fix ILP32 tbranch

[gcc r13-4680] AArch64: Fix ILP32 tbranch

[Tamar Christina]

https://gcc.gnu.org/g:69ec1e2065ac43eea44fdfa703cf027ce72a62da

commit r13-4680-g69ec1e2065ac43eea44fdfa703cf027ce72a62da
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Tue Dec 13 18:01:15 2022 +0000

    AArch64: Fix ILP32 tbranch
    
    the baremetal builds are currently broken because the shift ends up in the wrong
    representation if the mode is SImode and the shift amount if 31.   To fix this
    create the rtx constant with an explicit mode so the backend passes know which
    representation it needs to take.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.md (tbranch_<code><mode>3): Use gen_int_mode.

Diff:
---
 gcc/config/aarch64/aarch64.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d749c98eef6..6c27fb89e66 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -957,7 +957,7 @@
 {
   rtx bitvalue = gen_reg_rtx (<ZEROM>mode);
   rtx reg = gen_lowpart (<ZEROM>mode, operands[0]);
-  rtx val = GEN_INT (1UL << UINTVAL (operands[1]));
+  rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode);
   emit_insn (gen_and<zerom>3 (bitvalue, reg, val));
   operands[1] = const0_rtx;
   operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue,