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* [gcc r13-4772] RISC-V: Fix vwrite_csr.c and vread_csr.c
@ 2022-12-19  9:40 Kito Cheng
  0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2022-12-19  9:40 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:b346e77f4d7b482df78f119819b1e06a544ef515

commit r13-4772-gb346e77f4d7b482df78f119819b1e06a544ef515
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Dec 19 17:28:25 2022 +0800

    RISC-V: Fix vwrite_csr.c and vread_csr.c
    
    gcc/testsuite:
    
            * gcc.target/riscv/rvv/base/vread_csr.c: Use specific option
            instead.
            * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c  | 3 +--
 gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
index 69c9c1fa5ca..ac5484fb023 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O3" } */
-/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
index f9b4e8848df..830ddb95d16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O3" } */
-/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
 #include "riscv_vector.h"

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