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* [gcc r13-5138] aarch64: Fix DWARF frame register sizes for predicates
@ 2023-01-13 10:01 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-01-13 10:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:eb4994545fbd2a670e422f6e98c16e4ed60ac53e
commit r13-5138-geb4994545fbd2a670e422f6e98c16e4ed60ac53e
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Fri Jan 13 10:01:32 2023 +0000
aarch64: Fix DWARF frame register sizes for predicates
Jakub pointed out that __builtin_init_dwarf_reg_size_table
set the size of predicate registers to their current runtime
size when compiled with +sve, but to 8 bytes otherwise.
As explained in the comment, both behaviours are wrong.
Predicates change size with VL and should never need to be
restored during unwinding.
In contrast, the call-saved FP&SIMD frame registers are 8 bytes
(even though the hardware registers are at least 16 bytes) and
the call-clobbered registers have zero size. A zero size seems
correct for predicates too.
gcc/
* config/aarch64/aarch64.cc (aarch64_dwarf_frame_reg_mode): New
function.
(TARGET_DWARF_FRAME_REG_MODE): Define.
gcc/testsuite/
* gcc.target/aarch64/dwarf_reg_size_1.c: New test.
* gcc.target/aarch64/dwarf_reg_size_2.c: Likewise.
Diff:
---
gcc/config/aarch64/aarch64.cc | 17 ++++++++++++++
.../gcc.target/aarch64/dwarf_reg_size_1.c | 27 ++++++++++++++++++++++
.../gcc.target/aarch64/dwarf_reg_size_2.c | 6 +++++
3 files changed, 50 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 80b71a7b612..2821368756b 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -3443,6 +3443,20 @@ aarch64_debugger_regno (unsigned regno)
return DWARF_FRAME_REGISTERS;
}
+/* Implement TARGET_DWARF_FRAME_REG_MODE. */
+static machine_mode
+aarch64_dwarf_frame_reg_mode (int regno)
+{
+ /* Predicate registers are call-clobbered in the EH ABI (which is
+ ARM_PCS_AAPCS64), so they should not be described by CFI.
+ Their size changes as VL changes, so any values computed by
+ __builtin_init_dwarf_reg_size_table might not be valid for
+ all frames. */
+ if (PR_REGNUM_P (regno))
+ return VOIDmode;
+ return default_dwarf_frame_reg_mode (regno);
+}
+
/* If X is a CONST_DOUBLE, return its bit representation as a constant
integer, otherwise return X unmodified. */
static rtx
@@ -27900,6 +27914,9 @@ aarch64_libgcc_floating_mode_supported_p
#undef TARGET_SCHED_REASSOCIATION_WIDTH
#define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
+#undef TARGET_DWARF_FRAME_REG_MODE
+#define TARGET_DWARF_FRAME_REG_MODE aarch64_dwarf_frame_reg_mode
+
#undef TARGET_PROMOTED_TYPE
#define TARGET_PROMOTED_TYPE aarch64_promoted_type
diff --git a/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
new file mode 100644
index 00000000000..cb7666ddaa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-fbuilding-libgcc" } */
+
+static unsigned char dwarf_reg_size_table[__LIBGCC_DWARF_FRAME_REGISTERS__+1];
+
+int
+main (void)
+{
+ __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
+ /* X0-X31 and SP. */
+ for (int i = 0; i < 32; ++i)
+ if (dwarf_reg_size_table[i] != 8)
+ __builtin_abort ();
+ /* Q0-Q31/Z0-Z31, of which only the low 64 bits of register 8-15
+ are saved. */
+ for (int i = 64; i < 96; ++i)
+ if (dwarf_reg_size_table[i] != (i >= 72 && i < 80 ? 8 : 0))
+ __builtin_abort ();
+ /* P0-P15, which are never saved. */
+ for (int i = 48; i < 63; ++i)
+ if (dwarf_reg_size_table[i] != 0)
+ __builtin_abort ();
+ /* VG */
+ if (dwarf_reg_size_table[46] != 8)
+ __builtin_abort ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
new file mode 100644
index 00000000000..8b7e6d4a717
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-fbuilding-libgcc" } */
+
+#pragma GCC target "+sve"
+
+#include "dwarf_reg_size_1.c"
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