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* [gcc r13-6106] RISC-V: Move saturating add/subtract md pattern location [NFC]
@ 2023-02-17 2:47 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2023-02-17 2:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5804c20b13f28cf6c2e464003c338104bb508906
commit r13-6106-g5804c20b13f28cf6c2e464003c338104bb508906
Author: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date: Wed Feb 15 07:18:20 2023 +0800
RISC-V: Move saturating add/subtract md pattern location [NFC]
gcc/ChangeLog:
* config/riscv/vector.md (@pred_<optab><mode>): Rearrange.
(@pred_<optab><mode>_scalar): Ditto.
(*pred_<optab><mode>_scalar): Ditto.
(*pred_<optab><mode>_extended_scalar): Ditto.
Diff:
---
gcc/config/riscv/vector.md | 490 ++++++++++++++++++++++-----------------------
1 file changed, 245 insertions(+), 245 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cc550b7458b..6c02cf3d568 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1336,7 +1336,6 @@
;; - 11.9 Vector Integer Min/Max Instructions
;; - 11.10 Vector Single-Width Integer Multiply Instructions
;; - 11.11 Vector Integer Divide Instructions
-;; - 12.1 Vector Single-Width Saturating Add and Subtract
;; -------------------------------------------------------------------------------
(define_insn "@pred_<optab><mode>"
@@ -1728,248 +1727,6 @@
[(set_attr "type" "vialu")
(set_attr "mode" "<MODE>")])
-;; Saturating Add and Subtract
-(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
- (if_then_else:VI
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_sat_int_binop:VI
- (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr")
- (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
- (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))]
- "TARGET_VECTOR"
- "@
- v<insn>.vv\t%0,%3,%4%p1
- v<insn>.vv\t%0,%3,%4%p1
- v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
- v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
-(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr")
- (if_then_else:VI_QHS
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_plus_binop:VI_QHS
- (vec_duplicate:VI_QHS
- (match_operand:<VEL> 4 "register_operand" " r, r"))
- (match_operand:VI_QHS 3 "register_operand" " vr, vr"))
- (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr")
- (if_then_else:VI_QHS
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_minus_binop:VI_QHS
- (match_operand:VI_QHS 3 "register_operand" " vr, vr")
- (vec_duplicate:VI_QHS
- (match_operand:<VEL> 4 "register_operand" " r, r")))
- (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 5 "vector_length_operand")
- (match_operand 6 "const_int_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_plus_binop:VI_D
- (vec_duplicate:VI_D
- (match_operand:<VEL> 4 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand"))
- (match_operand:VI_D 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {
- if (riscv_vector::has_vi_variant_p (<CODE>, operands[4]))
- operands[4] = force_reg (<VEL>mode, operands[4]);
- else if (!TARGET_64BIT)
- {
- rtx v = gen_reg_rtx (<MODE>mode);
-
- if (immediate_operand (operands[4], Pmode))
- operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
- force_reg (Pmode, operands[4]));
- else
- {
- if (CONST_INT_P (operands[4]))
- operands[4] = force_reg (<VEL>mode, operands[4]);
-
- riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (<MODE>mode),
- v, operands[4], operands[5], <VM>mode);
- emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], v, operands[5],
- operands[6], operands[7], operands[8]));
- DONE;
- }
- }
- else
- operands[4] = force_reg (<VEL>mode, operands[4]);
- })
-
-(define_insn "*pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_plus_binop:VI_D
- (vec_duplicate:VI_D
- (match_operand:<VEL> 4 "register_operand" " r, r"))
- (match_operand:VI_D 3 "register_operand" " vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*pred_<optab><mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_plus_binop:VI_D
- (vec_duplicate:VI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 4 "register_operand" " r, r")))
- (match_operand:VI_D 3 "register_operand" " vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 5 "vector_length_operand")
- (match_operand 6 "const_int_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_minus_binop:VI_D
- (match_operand:VI_D 3 "register_operand")
- (vec_duplicate:VI_D
- (match_operand:<VEL> 4 "reg_or_int_operand")))
- (match_operand:VI_D 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {
- if (riscv_vector::has_vi_variant_p (<CODE>, operands[4]))
- operands[4] = force_reg (<VEL>mode, operands[4]);
- else if (!TARGET_64BIT)
- {
- rtx v = gen_reg_rtx (<MODE>mode);
-
- if (immediate_operand (operands[4], Pmode))
- operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
- force_reg (Pmode, operands[4]));
- else
- {
- if (CONST_INT_P (operands[4]))
- operands[4] = force_reg (<VEL>mode, operands[4]);
-
- riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (<MODE>mode),
- v, operands[4], operands[5], <VM>mode);
- emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
- operands[2], operands[3], v, operands[5],
- operands[6], operands[7], operands[8]));
- DONE;
- }
- }
- else
- operands[4] = force_reg (<VEL>mode, operands[4]);
- })
-
-(define_insn "*pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_minus_binop:VI_D
- (match_operand:VI_D 3 "register_operand" " vr, vr")
- (vec_duplicate:VI_D
- (match_operand:<VEL> 4 "register_operand" " r, r")))
- (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*pred_<optab><mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
- (if_then_else:VI_D
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (sat_int_minus_binop:VI_D
- (match_operand:VI_D 3 "register_operand" " vr, vr")
- (vec_duplicate:VI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 4 "register_operand" " r, r"))))
- (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
- "TARGET_VECTOR"
- "v<insn>.vx\t%0,%3,%4%p1"
- [(set_attr "type" "<int_binop_insn_type>")
- (set_attr "mode" "<MODE>")])
-
;; Multiply High instructions.
(define_insn "@pred_mulh<v_su><mode>"
[(set (match_operand:VFULLI 0 "register_operand" "=vd, vr")
@@ -3220,12 +2977,255 @@
;; ---- Predicated fixed-point operations
;; -------------------------------------------------------------------------------
;; Includes:
+;; - 12.1 Vector Single-Width Saturating Add and Subtract
;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
-;; - 12.5 Vector Single-Width Scaling Shift Instructions
-;; - 12.6 Vector Narrowing Fixed-Point Clip Instructions
+;; - 12.4 Vector Single-Width Scaling Shift Instructions
+;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
;; -------------------------------------------------------------------------------
+;; Saturating Add and Subtract
+(define_insn "@pred_<optab><mode>"
+ [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
+ (if_then_else:VI
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (any_sat_int_binop:VI
+ (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr")
+ (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
+ (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))]
+ "TARGET_VECTOR"
+ "@
+ v<insn>.vv\t%0,%3,%4%p1
+ v<insn>.vv\t%0,%3,%4%p1
+ v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+ v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
+(define_insn "@pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_QHS
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_plus_binop:VI_QHS
+ (vec_duplicate:VI_QHS
+ (match_operand:<VEL> 4 "register_operand" " r, r"))
+ (match_operand:VI_QHS 3 "register_operand" " vr, vr"))
+ (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_QHS
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_minus_binop:VI_QHS
+ (match_operand:VI_QHS 3 "register_operand" " vr, vr")
+ (vec_duplicate:VI_QHS
+ (match_operand:<VEL> 4 "register_operand" " r, r")))
+ (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "@pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_D 0 "register_operand")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand")
+ (match_operand 5 "vector_length_operand")
+ (match_operand 6 "const_int_operand")
+ (match_operand 7 "const_int_operand")
+ (match_operand 8 "const_int_operand")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_plus_binop:VI_D
+ (vec_duplicate:VI_D
+ (match_operand:<VEL> 4 "reg_or_int_operand"))
+ (match_operand:VI_D 3 "register_operand"))
+ (match_operand:VI_D 2 "vector_merge_operand")))]
+ "TARGET_VECTOR"
+ {
+ if (riscv_vector::has_vi_variant_p (<CODE>, operands[4]))
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+ else if (!TARGET_64BIT)
+ {
+ rtx v = gen_reg_rtx (<MODE>mode);
+
+ if (immediate_operand (operands[4], Pmode))
+ operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
+ force_reg (Pmode, operands[4]));
+ else
+ {
+ if (CONST_INT_P (operands[4]))
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+
+ riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (<MODE>mode),
+ v, operands[4], operands[5], <VM>mode);
+ emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
+ operands[2], operands[3], v, operands[5],
+ operands[6], operands[7], operands[8]));
+ DONE;
+ }
+ }
+ else
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+ })
+
+(define_insn "*pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_plus_binop:VI_D
+ (vec_duplicate:VI_D
+ (match_operand:<VEL> 4 "register_operand" " r, r"))
+ (match_operand:VI_D 3 "register_operand" " vr, vr"))
+ (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*pred_<optab><mode>_extended_scalar"
+ [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_plus_binop:VI_D
+ (vec_duplicate:VI_D
+ (sign_extend:<VEL>
+ (match_operand:<VSUBEL> 4 "register_operand" " r, r")))
+ (match_operand:VI_D 3 "register_operand" " vr, vr"))
+ (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "@pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_D 0 "register_operand")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand")
+ (match_operand 5 "vector_length_operand")
+ (match_operand 6 "const_int_operand")
+ (match_operand 7 "const_int_operand")
+ (match_operand 8 "const_int_operand")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_minus_binop:VI_D
+ (match_operand:VI_D 3 "register_operand")
+ (vec_duplicate:VI_D
+ (match_operand:<VEL> 4 "reg_or_int_operand")))
+ (match_operand:VI_D 2 "vector_merge_operand")))]
+ "TARGET_VECTOR"
+ {
+ if (riscv_vector::has_vi_variant_p (<CODE>, operands[4]))
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+ else if (!TARGET_64BIT)
+ {
+ rtx v = gen_reg_rtx (<MODE>mode);
+
+ if (immediate_operand (operands[4], Pmode))
+ operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
+ force_reg (Pmode, operands[4]));
+ else
+ {
+ if (CONST_INT_P (operands[4]))
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+
+ riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (<MODE>mode),
+ v, operands[4], operands[5], <VM>mode);
+ emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
+ operands[2], operands[3], v, operands[5],
+ operands[6], operands[7], operands[8]));
+ DONE;
+ }
+ }
+ else
+ operands[4] = force_reg (<VEL>mode, operands[4]);
+ })
+
+(define_insn "*pred_<optab><mode>_scalar"
+ [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_minus_binop:VI_D
+ (match_operand:VI_D 3 "register_operand" " vr, vr")
+ (vec_duplicate:VI_D
+ (match_operand:<VEL> 4 "register_operand" " r, r")))
+ (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*pred_<optab><mode>_extended_scalar"
+ [(set (match_operand:VI_D 0 "register_operand" "=vd, vr")
+ (if_then_else:VI_D
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (sat_int_minus_binop:VI_D
+ (match_operand:VI_D 3 "register_operand" " vr, vr")
+ (vec_duplicate:VI_D
+ (sign_extend:<VEL>
+ (match_operand:<VSUBEL> 4 "register_operand" " r, r"))))
+ (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))]
+ "TARGET_VECTOR"
+ "v<insn>.vx\t%0,%3,%4%p1"
+ [(set_attr "type" "<int_binop_insn_type>")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "@pred_<sat_op><mode>"
[(set (match_operand:VI 0 "register_operand" "=vd, vr")
(if_then_else:VI
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2023-02-17 2:47 [gcc r13-6106] RISC-V: Move saturating add/subtract md pattern location [NFC] Kito Cheng
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