[gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers.

[gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:e7668c50a5c0b069669e40159089dbb60db8392c

commit e7668c50a5c0b069669e40159089dbb60db8392c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 13:53:07 2023 -0400

    Enhance vec_extract from int memory with constant element numbers.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    Without this patch, the compiler would load the value into a GPR register and
    then do a direct move if it needs the value in a vector register.
    
    2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..0e681844243 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3567,6 +3567,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,m,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p8v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")

[gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:99bd3be639dee32eaed78afc4dbb069263d20ea4

commit 99bd3be639dee32eaed78afc4dbb069263d20ea4
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 18 01:39:39 2023 -0400

    Enhance vec_extract from int memory with constant element numbers.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    Without this patch, the compiler would load the value into a GPR register and
    then do a direct move if it needs the value in a vector register.
    
    2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 33 ++++++++++++----
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 44 ++++++++++++++++++++++
 2 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..26caf81b01b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3930,13 +3930,31 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
+	(vec_select:SI
+	 (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
+	 (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3945,8 +3963,9 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")
+   (set_attr "isa" "*,*,p9v,p9v")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..209ca926b97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode directly into vector registers.  */
+
+#include <altivec.h>
+
+void
+extract_sign_v4si_0 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_sign_v4si_1 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_v4si_1 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlfiw[az]x\M|\mlxsiw[az]x\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mlw[az]x\M}                    } } */
+/* { dg-final { scan-assembler-not   {\mmtvsrw[sz]\M}                 } } */

[gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:986cea0b6fdd6f180a1276907790f81cc4e6f8dc

commit 986cea0b6fdd6f180a1276907790f81cc4e6f8dc
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 17 18:35:11 2023 -0400

    Enhance vec_extract from int memory with constant element numbers.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    Without this patch, the compiler would load the value into a GPR register and
    then do a direct move if it needs the value in a vector register.
    
    2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 33 ++++++++++++----
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 44 ++++++++++++++++++++++
 2 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..26caf81b01b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3930,13 +3930,31 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
+	(vec_select:SI
+	 (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
+	 (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3945,8 +3963,9 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")
+   (set_attr "isa" "*,*,p9v,p9v")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..0be1d471ac5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode directly into vector registers.  */
+
+#include <altivec.h>
+
+void
+extract_sign_v4si_0 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_sign_v4si_1 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_v4si_1 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\ml(f|xs)iw[az]x\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mlw[az]x\M}          } } */
+/* { dg-final { scan-assembler-not   {\mmtvsrw[sz]\M}       } } */

[gcc(refs/users/meissner/heads/work119)] Enhance vec_extract from int memory with constant element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:5ec8cf2151220c14043b19cdfee8e6fc1b85e49c

commit 5ec8cf2151220c14043b19cdfee8e6fc1b85e49c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 17 18:05:17 2023 -0400

    Enhance vec_extract from int memory with constant element numbers.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    Without this patch, the compiler would load the value into a GPR register and
    then do a direct move if it needs the value in a vector register.
    
    2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-int-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 33 +++++++++++++----
 .../gcc.target/powerpc/vec-extract-mem-int-1.c     | 43 ++++++++++++++++++++++
 2 files changed, 69 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..26caf81b01b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3930,13 +3930,31 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V4SI element from memory with constant element number.
+(define_insn_and_split "*vsx_extract_v4si_load"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,wa,wa")
+	(vec_select:SI
+	 (match_operand:V4SI 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SImode);
+}
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")])
+
+;; Extract a V8HI/V16QI element from memory with constant element number.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,v,v")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
+	 (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3945,8 +3963,9 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "4,8,4,8")
+   (set_attr "isa" "*,*,p9v,p9v")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..db7ea3300e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   SImode directly into vector registers.  */
+
+#include <altivec.h>
+
+void
+extract_sign_v4si_0 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_sign_v4si_1 (vector int *p, int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_uns_v4si_0 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 0);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+void
+extract_v4si_1 (vector unsigned int *p, unsigned int *q)
+{
+  int x = vec_extract (*p, 1);
+  __asm__ (" # %x0" : "+wa" (x));	/* lfiwzx or lfiwax.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlfiw[az]x\M} 4 } } */
+/* { dg-final { scan-assembler-not   {\mlw[az]x\M}     } } */