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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert. Date: Wed, 19 Apr 2023 19:25:21 +0000 (GMT) [thread overview] Message-ID: <20230419192521.1A2E63858D33@sourceware.org> (raw) https://gcc.gnu.org/g:354e5bb1234064a4a5a0cb88061470738107668f commit 354e5bb1234064a4a5a0cb88061470738107668f Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Apr 19 15:24:36 2023 -0400 Combine vec_extract of V4SF with DF convert. This patch adds a combine insn that merges loading up a vec_extract of V4SFmode where the element number is constant combined with a conversion to DFmode. 2023-04-18 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn. Diff: --- gcc/config/rs6000/vsx.md | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0e681844243..c3b870640ed 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -3951,23 +3957,28 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number. +;; If the element number is 0, we don't need to do a load immediate operation. +;; Likewise for GPRs with offsettable loads, we can fold the offset into the +;; address. For vector registers, we are limited to X-FORM memory addresses. +;; PowerPC64 is needed because we need a DI temporary base register. (define_insn_and_split "*vsx_extract_<mode>_load" - [(set (match_operand:<VEC_base> 0 "register_operand" "=r") + [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>") (vec_select:<VEC_base> - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] - "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT" + (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q") + (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")]))) + (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))] + "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], <VEC_base>mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load,load,load,fpload,fpload") + (set_attr "length" "4,4,8,4,8") + (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract_<mode>_var"
next reply other threads:[~2023-04-19 19:25 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-19 19:25 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2023-04-21 21:05 Michael Meissner 2023-04-21 19:55 Michael Meissner 2023-04-21 19:44 Michael Meissner 2023-04-21 19:04 Michael Meissner 2023-04-21 18:57 Michael Meissner 2023-04-19 19:32 Michael Meissner 2023-04-19 19:18 Michael Meissner
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