[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:63e61c4651301839e07e8e2818a174774476d8af

commit 63e61c4651301839e07e8e2818a174774476d8af
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 17:04:38 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.  I also
    simplified the alternatives.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 38 +++++++++++++++++-----
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 31 ++++++++++++++++++
 2 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..17e56ab1ce4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,23 +3549,45 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.  If
+;; the element number is 0, we don't need a temporary register.
 (define_insn_and_split "*vsx_extract_v4sf_load"
-  [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
+  [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
 	(vec_select:SF
-	 (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
-	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
-   (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
+	 (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
+	 (parallel
+	  [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
+   (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], SFmode);
 }
-  [(set_attr "type" "fpload,fpload,fpload,load")
-   (set_attr "length" "8")
-   (set_attr "isa" "*,p7v,p9v,*")])
+  [(set_attr "type" "fpload,fpload,load,load")
+   (set_attr "length" "4,8,4,8")])
+
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=wa,wa")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Q")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
+   (clobber (match_scratch:P 3 "=X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "4,8")])
 
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..34ebc574339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+
+void
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+void
+extract_float_1_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 1);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mm[tf]vsd}              } } */
+/* { dg-final { scan-assembler-not   {\mxscvdpspn?\M}          } } */