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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.
Date: Fri, 21 Apr 2023 19:04:24 +0000 (GMT) [thread overview]
Message-ID: <20230421190424.32DCE3858C83@sourceware.org> (raw)
https://gcc.gnu.org/g:5a5c396c1052046c96e5e823eee80c05ef53b0a5
commit 5a5c396c1052046c96e5e823eee80c05ef53b0a5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:04:07 2023 -0400
Combine vec_extract of V4SF with DF convert.
This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
where the element number is constant combined with a conversion to DFmode.
In addition, I changed the vec_extract of V4SFmode where the element number is
constant without conversion to do the split before register allocation.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
register allocation.
(vsx_extract_v4sf_to_df_load): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-1.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 24 +++++++++++++++++-
| 29 ++++++++++++++++++++++
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..c3848de5d4f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
+;; V4SF extract from memory convert to DFmode with constant element number.
(define_insn_and_split "*vsx_extract_v4sf_load"
[(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
@@ -3557,7 +3558,7 @@
(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3567,6 +3568,27 @@
(set_attr "length" "8")
(set_attr "isa" "*,p7v,p9v,*")])
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+ [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+ (float_extend:DF
+ (vec_select:SF
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+ (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode)"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v")])
+
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..eab7892ed80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ float (SF) variables into a GPR without doing a LFS or STFS. */
+
+#include <altivec.h>
+
+float
+extract_float_0_gpr (vector float *p, float *q)
+{
+ float x = vec_extract (*p, 0);
+ __asm__ ("# %0" : "+r" (x)); /* lwz. */
+ *q = x;
+}
+
+float
+extract_float_3_gpr (vector float *p, float *q)
+{
+ float x = vec_extract (*p, 3);
+ __asm__ ("# %0" : "+r" (x)); /* lwz. */
+ *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
+/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
next reply other threads:[~2023-04-21 19:04 UTC|newest]
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2023-04-21 19:04 Michael Meissner [this message]
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