[gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:5dddad51364149a704e8271379b0962b4bcf6790

commit 5dddad51364149a704e8271379b0962b4bcf6790
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 00:05:19 2023 -0400

    Allow vec_extract with variable element number to load vector registers.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
            of integer types with a variable element number to load into vector
            registers.  Allow splitting before register allocation.

Diff:
---
 gcc/config/rs6000/vsx.md | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b234b807087..d6b72a2fe33 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4127,21 +4127,23 @@
 
 ;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+	  (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b"))]
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "12,16,12,16")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"