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* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers.
@ 2023-04-21 4:05 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 4:05 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5dddad51364149a704e8271379b0962b4bcf6790
commit 5dddad51364149a704e8271379b0962b4bcf6790
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 00:05:19 2023 -0400
Allow vec_extract with variable element number to load vector registers.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
of integer types with a variable element number to load into vector
registers. Allow splitting before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b234b807087..d6b72a2fe33 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4127,21 +4127,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "12,16,12,16")
+ (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers.
@ 2023-04-21 3:12 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 3:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0c9e5ca8705c37db519064652aec3b649e32ba50
commit 0c9e5ca8705c37db519064652aec3b649e32ba50
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 23:11:50 2023 -0400
Allow vec_extract with variable element number to load vector registers.
2023-04-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
of integer types with a variable element number to load into vector
registers. Allow splitting before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c5c2920fcd1..fd17d0c29f1 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4124,21 +4124,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r,<VSX_EX>,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,m,Q,m")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r,r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,load,fpload,fpload")
+ (set_attr "length" "4,8,4,8")
+ (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow vec_extract with variable element number to load vector registers.
@ 2023-04-21 2:56 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 2:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:81edfbf6be5a334165f848bf9f2548780296df7a
commit 81edfbf6be5a334165f848bf9f2548780296df7a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 20 22:56:24 2023 -0400
Allow vec_extract with variable element number to load vector registers.
2023-04-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
of integer types with a variable element number to load into vector
registers. Allow splitting before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c5c2920fcd1..d4d00a3d637 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4124,21 +4124,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 3+ messages in thread
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