[gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers.

[gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers.

[Michael Meissner]

https://gcc.gnu.org/g:b7348c952a9cbc0b3bc9402c2e9187c4ea763c48

commit b7348c952a9cbc0b3bc9402c2e9187c4ea763c48
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 19:48:36 2023 -0400

    Allow integer vec_extract to load vector registers.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
            (vsx_extract_<mode>_load): Allow vec_extract of integer types with a
            constant element number to load into vector registers.  Don't require a
            base register temporary if the element number is 0.

Diff:
---
 gcc/config/rs6000/vsx.md | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 04877dd51f6..9d76217f84c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+			      (V8HI  "p9v")
+			      (V4SI  "p8v")])
+
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3971,13 +3977,15 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element
+;; number.  If the element number is 0, we don't need a temporary base
+;; register.  For vector registers, we require X-form addressing.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,<VSX_EX>,<VSX_EX>")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,Q,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "O,n,O,n")])))
+   (clobber (match_scratch:DI 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3986,8 +3994,9 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,fpload,fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"