[gcc(refs/users/meissner/heads/work119)] Fold sign/zero extension into V8HI vsx_extract from memory with constant element.

[gcc(refs/users/meissner/heads/work119)] Fold sign/zero extension into V8HI vsx_extract from memory with constant element.

[Michael Meissner]

https://gcc.gnu.org/g:58533ad32aa7aaaaf05cad5ff340337e60a4c406

commit 58533ad32aa7aaaaf05cad5ff340337e60a4c406
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 20:47:55 2023 -0400

    Fold sign/zero extension into V8HI vsx_extract from memory with constant element.
    
    This patch folds V8HI vsx_extract from memory where the element number is
    constant with sign or zero extension to SImode/DImode.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v8hi_load_to_<su><mode>): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5fb77e9cc22..8e9c9955139 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4019,6 +4019,27 @@
   [(set_attr "type" "load,load,fpload,fpload")
    (set_attr "length" "8")])
 
+;; Extract a V8HI element from memory with a constant element number and sign
+;; or zero extend it to either SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_<su><mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=r,r")
+	(any_extend:GPR
+	 (vec_select:HI
+	  (match_operand:V8HI 1 "memory_operand" "m,Q")
+	  (parallel [(match_operand:QI 2 "const_0_to_7_operand" "O,n")]))))
+   (clobber (match_scratch:DI 3 "=X,&b"))]
+  "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(any_extend:GPR (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], HImode);
+}
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
+
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
   [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")