[gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers for variable element numbers.

[gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers for variable element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:97b99dca4bc0e0b3c5770a368f301c8c537a76b1

commit 97b99dca4bc0e0b3c5770a368f301c8c537a76b1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Apr 22 01:51:01 2023 -0400

    Allow integer vec_extract to load vector registers for variable element numbers.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
            of integer types with a constant element number to load into vector
            registers.

Diff:
---
 gcc/config/rs6000/vsx.md | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60f47d748a6..c49c323faeb 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4083,12 +4083,12 @@
 
 ;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+	  (match_operand:DI 2 "gpc_reg_operand" "r,r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b"))]
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -4097,7 +4097,8 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load,fpload")
+   (set_attr "isa" "*,<VSX_EX_ISA>")])
 
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"

[gcc(refs/users/meissner/heads/work119)] Allow integer vec_extract to load vector registers for variable element numbers.

[Michael Meissner]

https://gcc.gnu.org/g:ce5fa8bf2140707ef44cbf30d643d673b502c738

commit ce5fa8bf2140707ef44cbf30d643d673b502c738
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Apr 22 01:45:56 2023 -0400

    Allow integer vec_extract to load vector registers for variable element numbers.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vec_extract
            of integer types with a constant element number to load into vector
            registers.

Diff:
---
 gcc/config/rs6000/vsx.md | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60f47d748a6..d088936915d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4083,12 +4083,12 @@
 
 ;; Variable V16QI/V8HI/V4SI extract from memory
 (define_insn_and_split "*vsx_extract_<mode>_var_load"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
 	(unspec:<VEC_base>
-	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
-	  (match_operand:DI 2 "gpc_reg_operand" "r")]
+	 [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+	  (match_operand:DI 2 "gpc_reg_operand" "r,r")]
 	 UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=&b"))]
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -4097,7 +4097,8 @@
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")])
+  [(set_attr "type" "load")
+   (set_attr "isa" "*,<VSX_EX_ISA>")])
 
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"