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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner Date: Tue, 25 Apr 2023 02:55:20 +0000 (GMT) [thread overview] Message-ID: <20230425025520.1D3D53858D1E@sourceware.org> (raw) https://gcc.gnu.org/g:ade6286b050123ef8fcd9ff15e435bed8bd77e38 commit ade6286b050123ef8fcd9ff15e435bed8bd77e38 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon Apr 24 22:55:16 2023 -0400 Update ChangeLog.meissner Diff: --- gcc/ChangeLog.meissner | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 1fe1b591c74..3334848781f 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,40 @@ +==================== Branch work119, patch #83 ==================== + +Allow variable element vec_extract to be sign or zero extended + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +variable element number to be loaded with sign or zero extension, and GCC will +not generate a separate zero/sign extension instruction. + +2023-04-24 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn. + (vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn. + (vsx_extract_v8hi_var_load_to_s<mode>): New insn. + +gcc/testsuite/ + + * gcc.target/powerpc/vec-extract-mem-int-3.c: New file. + * gcc.target/powerpc/vec-extract-mem-short-3.c: New file. + + +==================== Branch work119, patch #82 ==================== + +Allow variable element vec_extract to be loaded into vector registers. + +This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a +variable element number to be loaded into vector registers directly. It also +will be split before register allocation. + +2023-04-24 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector + registers to be loaded. Split before register allocation. + ==================== Branch work119, patch #81 ==================== Allow consant element vec_extract to be zero or sign extended
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