[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.meissner

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:254a02cd8df1afb9393c2526473d9254debdebcd

commit 254a02cd8df1afb9393c2526473d9254debdebcd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 27 23:44:41 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b82c649fdf6..514c593ada8 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,33 @@
+==================== Branch work119, patch #97 ====================
+
+Allow constant element vec_extract to be converted to floating point
+
+This patch allows vec_extract of the following types to be converted to
+floating point by loading the value directly to the vector register, and then
+doing the conversion instead of loading the value to a GPR and then doing a
+direct move:
+
+	vector int
+	vector unsigned int
+	vector unsigned short
+	vector unsigned char
+
+2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.md (fp_int_extend): New code attribute.
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<uns><mode>): New
+	* insn.
+	* vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>: New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-2.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-int_5.c: New file.
+	* gcc.target/powerpc/vec-extract-mem-short-4.c: New file.
+
 ==================== Branch work119, patch #96 ====================
 
 Allow variable element vec_extract to be sign or zero extended
@@ -19,7 +49,6 @@ gcc/testsuite/
 	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
 	* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
 
-
 ==================== Branch work119, patch #95 ====================
 
 Allow variable element vec_extract to be loaded into vector registers.