[gcc(refs/users/meissner/heads/work119)] Optimize vec_extract of V4SF with variable element number being converted to DF

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:9d4c959c2bf6ff9f2eb8834d1652bdddc2519e66

commit 9d4c959c2bf6ff9f2eb8834d1652bdddc2519e66
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 27 16:43:41 2023 -0400

    Optimize vec_extract of V4SF with variable element number being converted to DF
    
    This patch adds a combiner insn to include the conversion of float to double
    within the memory address when vec_extract of V4SF with a variable element
    number is done.
    
    In addition, the patch allows the split of vec_extract of V4SF with a variable
    element number to occur before register allocation.
    
    2023-04-27   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_var_load_to_df): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 695b5cbd126..3a4b8cdb02a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,7 +3607,7 @@
   DONE;
 })
 
-;; Variable V4SF extract from memory
+;; V4SF extract from memory with variable element number.
 (define_insn_and_split "*vsx_extract_v4sf_var_load"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
 	(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3616,7 +3616,7 @@
    (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,6 +3624,25 @@
 }
   [(set_attr "type" "fpload,load")])
 
+;; V4SF extract from memory with variable element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+	(float_extend:DF
+	 (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+		     (match_operand:DI 2 "gpc_reg_operand" "r")]
+		    UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")])
+
 ;; Expand the builtin form of xxpermdi to canonical rtl.
 (define_expand "vsx_xxpermdi_<mode>"
   [(match_operand:VSX_L 0 "vsx_register_operand")