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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Optimize vec_extract of V4SF with variable element number being converted to DF
Date: Sat, 29 Apr 2023 02:48:04 +0000 (GMT) [thread overview]
Message-ID: <20230429024804.52F033858D37@sourceware.org> (raw)
https://gcc.gnu.org/g:3edb1d030892c4074609494f626cba437eaa6ae7
commit 3edb1d030892c4074609494f626cba437eaa6ae7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 22:47:44 2023 -0400
Optimize vec_extract of V4SF with variable element number being converted to DF
This patch adds a combiner insn to include the conversion of float to double
within the memory address when vec_extract of V4SF with a variable element
number is done.
It also removes the '?' from the 'r' constraint so that if the SFmode is needed
in a GPR, it doesn't have to load it to the vector unit and then store it.
2023-04-28 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Remove '?' from 'r'
constraint.
(vsx_extract_v4sf_var_load_to_df): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 21 ++++++++++++++++++++-
| 22 ++++++++++++++++++++++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9d3b3441ed5..f42793fe012 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3646,7 +3646,7 @@
;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
@@ -3661,6 +3661,25 @@
}
[(set_attr "type" "fpload,load")])
+;; V4SF extract from memory with variable element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+ (float_extend:DF
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")])
+
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..2561aa930b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ float elements into a GPR register without doing a LFS/STFS. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+void
+extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
+{
+ float x = vec_extract (*p, n);
+ __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
+ *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
+/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
next reply other threads:[~2023-04-29 2:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-29 2:48 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-04-29 0:09 Michael Meissner
2023-04-28 22:21 Michael Meissner
2023-04-28 18:04 Michael Meissner
2023-04-27 21:58 Michael Meissner
2023-04-27 20:44 Michael Meissner
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