[gcc(refs/users/meissner/heads/work119)] Optimize vec_extract of V4SF with variable element number being converted to DF

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:6ae84406009ffdb652e64382d9b2646c54859c5e

commit 6ae84406009ffdb652e64382d9b2646c54859c5e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 28 14:04:21 2023 -0400

    Optimize vec_extract of V4SF with variable element number being converted to DF
    
    This patch adds a combiner insn to include the conversion of float to double
    within the memory address when vec_extract of V4SF with a variable element
    number is done.
    
    In addition, the patch allows the split of vec_extract of V4SF with a variable
    element number to occur before register allocation.  In doing so, I restricted
    the optimization to only occur if the memory address did not use an Altivec
    style address with AND -16.
    
    2023-04-28   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
            register allocation.  Restrict memory addresses to not using Altivec
            memory addresses.
            (vsx_extract_v4sf_var_load_to_df): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-2.c: New file.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 25 +++++++++++++++++++---
 .../gcc.target/powerpc/vec-extract-mem-float-2.c   | 22 +++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ed4636f1e06..42336bbf36b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,16 +3607,16 @@
   DONE;
 })
 
-;; Variable V4SF extract from memory
+;; V4SF extract from memory with variable element number.
 (define_insn_and_split "*vsx_extract_v4sf_var_load"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
-	(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
+	(unspec:SF [(match_operand:V4SF 1 "non_altivec_memory_operand" "Q,Q")
 		    (match_operand:DI 2 "gpc_reg_operand" "r,r")]
 		   UNSPEC_VSX_EXTRACT))
    (clobber (match_scratch:DI 3 "=&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,6 +3624,25 @@
 }
   [(set_attr "type" "fpload,load")])
 
+;; V4SF extract from memory with variable element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+	(float_extend:DF
+	 (unspec:SF [(match_operand:V4SF 1 "non_altivec_memory_operand" "Q")
+		     (match_operand:DI 2 "gpc_reg_operand" "r")]
+		    UNSPEC_VSX_EXTRACT)))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")])
+
 ;; Expand the builtin form of xxpermdi to canonical rtl.
 (define_expand "vsx_xxpermdi_<mode>"
   [(match_operand:VSX_L 0 "vsx_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..2561aa930b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+   float elements into a GPR register without doing a LFS/STFS.  */
+
+#include <altivec.h>
+#include <stddef.h>
+
+void
+extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
+{
+  float x = vec_extract (*p, n);
+  __asm__ (" # %0" : "+r" (x));		/* lwz, no lfs/stfs.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M}               1 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}                 1 } } */
+/* { dg-final { scan-assembler-not   {\mlfsx?\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfsx?\M|\mstxsspx?\M}   } } */