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* [gcc(refs/users/meissner/heads/work120)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-05-01 21:46 Michael Meissner
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From: Michael Meissner @ 2023-05-01 21:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cf6c9e6421d08e310767571d97c8b3967a7ba0c2
commit cf6c9e6421d08e310767571d97c8b3967a7ba0c2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 1 17:46:24 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly.
2023-05-1 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9c3e07fbfce..65bec8e1d5f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4159,23 +4159,25 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,wa")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
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