[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)

[Jeff Law]

https://gcc.gnu.org/g:2b281ab46a9fe030ed9aae72f5ec624275e9e168

commit 2b281ab46a9fe030ed9aae72f5ec624275e9e168
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed May 31 18:43:44 2023 +0800

    RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)
    
    Base on the discussion here:
    https://github.com/riscv/riscv-v-spec/issues/884
    
    vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Remove FRM.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 60f052bcec9..cb4e77e7854 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7159,10 +7159,8 @@
 	     (match_operand 5 "const_int_operand"            "    i,    i")
 	     (match_operand 6 "const_int_operand"            "    i,    i")
 	     (match_operand 7 "const_int_operand"            "    i,    i")
-	     (match_operand 8 "const_int_operand"            "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_float:VF
 	     (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VF 2 "vector_merge_operand"         "   vu,    0")))]

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)

[Jeff Law]

https://gcc.gnu.org/g:758c6e9614cc7bce13c7681fa38930b00bb410dd

commit 758c6e9614cc7bce13c7681fa38930b00bb410dd
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed May 31 18:43:44 2023 +0800

    RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)
    
    Base on the discussion here:
    https://github.com/riscv/riscv-v-spec/issues/884
    
    vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Remove FRM.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 60f052bcec9..cb4e77e7854 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7159,10 +7159,8 @@
 	     (match_operand 5 "const_int_operand"            "    i,    i")
 	     (match_operand 6 "const_int_operand"            "    i,    i")
 	     (match_operand 7 "const_int_operand"            "    i,    i")
-	     (match_operand 8 "const_int_operand"            "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_float:VF
 	     (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VF 2 "vector_merge_operand"         "   vu,    0")))]