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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one potential test failure for RVV vsetvl
@ 2023-06-12 14:27 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-06-12 14:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a97440f879f5f3c8cdcaa1dc443a8a7512d74347
commit a97440f879f5f3c8cdcaa1dc443a8a7512d74347
Author: Pan Li <pan2.li@intel.com>
Date: Mon Jun 12 20:07:24 2023 +0800
RISC-V: Fix one potential test failure for RVV vsetvl
The test will fail on below command with multi-thread like below. However,
it comes from one missed "Oz" option when check vsetvl.
make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
or make without -j option. We would like to fix it and root cause the
reason later.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index 66c90ac10e7..f3420be8ab6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one potential test failure for RVV vsetvl
@ 2023-07-14 2:45 Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-07-14 2:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:285c0cf4809553e65643d2adce69cae21d10cc52
commit 285c0cf4809553e65643d2adce69cae21d10cc52
Author: Pan Li <pan2.li@intel.com>
Date: Mon Jun 12 20:07:24 2023 +0800
RISC-V: Fix one potential test failure for RVV vsetvl
The test will fail on below command with multi-thread like below. However,
it comes from one missed "Oz" option when check vsetvl.
make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
or make without -j option. We would like to fix it and root cause the
reason later.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index 66c90ac10e7..f3420be8ab6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
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2023-06-12 14:27 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Fix one potential test failure for RVV vsetvl Jeff Law
2023-07-14 2:45 Jeff Law
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