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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work122)] Revert patches Date: Tue, 13 Jun 2023 18:00:18 +0000 (GMT) [thread overview] Message-ID: <20230613180018.5D61D3858D38@sourceware.org> (raw) https://gcc.gnu.org/g:e5efbdc991534f471b5de41559764bb98922f9b5 commit e5efbdc991534f471b5de41559764bb98922f9b5 Author: Michael Meissner <meissner@linux.ibm.com> Date: Tue Jun 13 14:00:14 2023 -0400 Revert patches Diff: --- gcc/config/rs6000/fusion.md | 23 ++++++-------- gcc/config/rs6000/genfusion.pl | 37 +++------------------- gcc/config/rs6000/predicates.md | 14 ++++++++ gcc/config/rs6000/rs6000.md | 4 +-- gcc/testsuite/g++.target/powerpc/pr105325.C | 26 --------------- .../gcc.target/powerpc/fusion-p10-ldcmpi.c | 14 ++++---- 6 files changed, 37 insertions(+), 81 deletions(-) diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 9eefae22a1a..d45fb138a70 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -22,7 +22,7 @@ ;; load mode is DI result mode is clobber compare mode is CC extend is none (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_m1_to_1_operand" "n"))) (clobber (match_scratch:DI 0 "=r"))] "(TARGET_P10_FUSION)" @@ -43,7 +43,7 @@ ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") - (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_0_to_1_operand" "n"))) (clobber (match_scratch:DI 0 "=r"))] "(TARGET_P10_FUSION)" @@ -64,7 +64,7 @@ ;; load mode is DI result mode is DI compare mode is CC extend is none (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") + (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] "(TARGET_P10_FUSION)" @@ -85,7 +85,7 @@ ;; load mode is DI result mode is DI compare mode is CCUNS extend is none (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") - (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") + (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m") (match_operand:DI 3 "const_0_to_1_operand" "n"))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] "(TARGET_P10_FUSION)" @@ -106,22 +106,21 @@ ;; load mode is SI result mode is clobber compare mode is CC extend is none (define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") + (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) - (clobber (match_scratch:DI 0 "=r"))] + (clobber (match_scratch:SI 0 "=r"))] "(TARGET_P10_FUSION)" "lwa%X1 %0,%1\;cmpdi %2,%0,%3" "&& reload_completed && (cc_reg_not_cr0_operand (operands[2], CCmode) || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), SImode, NON_PREFIXED_DS))" - [(set (match_dup 0) (sign_extend:DI (match_dup 1))) + [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (compare:CC (match_dup 0) (match_dup 3)))] "" [(set_attr "type" "fused_load_cmpi") (set_attr "cost" "8") - (set_attr "sign_extend" "yes") (set_attr "length" "8")]) ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 @@ -149,7 +148,7 @@ ;; load mode is SI result mode is SI compare mode is CC extend is none (define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") + (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] "(TARGET_P10_FUSION)" @@ -158,13 +157,12 @@ && (cc_reg_not_cr0_operand (operands[2], CCmode) || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), SImode, NON_PREFIXED_DS))" - [(set (match_dup 0) (sign_extend:DI (match_dup 1))) + [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (compare:CC (match_dup 0) (match_dup 3)))] "" [(set_attr "type" "fused_load_cmpi") (set_attr "cost" "8") - (set_attr "sign_extend" "yes") (set_attr "length" "8")]) ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 @@ -192,7 +190,7 @@ ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") + (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m") (match_operand:SI 3 "const_m1_to_1_operand" "n"))) (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] "(TARGET_P10_FUSION)" @@ -207,7 +205,6 @@ "" [(set_attr "type" "fused_load_cmpi") (set_attr "cost" "8") - (set_attr "sign_extend" "yes") (set_attr "length" "8")]) ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 31ee54aea93..82e8f863b02 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -61,23 +61,15 @@ sub gen_ld_cmpi_p10_one my $mempred = "non_update_memory_operand"; my $extend; - # We need to special case lwa. The prefixed_load_p function in rs6000.cc - # (which determines if a load instruction is prefixed) uses the fact that the - # register mode is different from the memory mode, and that the sign_extend - # attribute is set to use DS-form rules for the address instead of D-form. - # If the register size is the same, prefixed_load_p assumes we are doing a - # lwz. - my $lwa_insn = ($lmode eq "SI" && $ccmode eq "CC"); - if ($ccmode eq "CC") { # ld and lwa are both DS-FORM. ($lmode =~ /^[SD]I$/) and $np = "NON_PREFIXED_DS"; -# ($lmode =~ /^[SD]I$/) and $mempred = "ds_form_mem_operand"; + ($lmode =~ /^[SD]I$/) and $mempred = "ds_form_mem_operand"; } else { if ($lmode eq "DI") { # ld is DS-form, but lwz is not. $np = "NON_PREFIXED_DS"; - # $mempred = "ds_form_mem_operand"; + $mempred = "ds_form_mem_operand"; } } @@ -89,9 +81,7 @@ sub gen_ld_cmpi_p10_one # For clobber, we need a SI/DI reg in case we # split because we have to sign/zero extend. - my $clobbermode = (($lmode =~ /^[QH]I$/) - ? "GPR" - : ($lwa_insn ? "DI" : $lmode)); + my $clobbermode = ($lmode =~ /^[QH]I$/) ? "GPR" : $lmode; if ($result =~ /^EXT/ || $result eq "GPR" || $clobbermode eq "GPR") { # We always need extension if result > lmode. $extend = ($ccmode eq "CC") ? "sign" : "zero"; @@ -101,15 +91,12 @@ sub gen_ld_cmpi_p10_one } my $ldst = mode_to_ldst_char($lmode); - - # DS-form addresses need YZ, and not m. - my $constraint = ($np eq "NON_PREFIXED_DS") ? "YZ" : "m"; print <<HERE; ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 ;; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend (define_insn_and_split "*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}" [(set (match_operand:${ccmode} 2 "cc_reg_operand" "=x") - (compare:${ccmode} (match_operand:${lmode} 1 "${mempred}" "${constraint}") + (compare:${ccmode} (match_operand:${lmode} 1 "${mempred}" "m") HERE print " " if $ccmode eq "CCUNS"; print <<HERE; @@ -139,12 +126,7 @@ HERE ${lmode}mode, ${np}))" HERE - # prefixed_load_p needs to see the register mode being different than the - # memory insn in order to validate lwa as a DS-form instruction and not a - # D-form instruction. - if ($lwa_insn && $extend eq "none") { - print " [(set (match_dup 0) (sign_extend:${clobbermode} (match_dup 1)))\n"; - } elsif ($extend eq "none") { + if ($extend eq "none") { print " [(set (match_dup 0) (match_dup 1))\n"; } elsif ($result eq "clobber") { print " [(set (match_dup 0) (${extend}_extend:${clobbermode} (match_dup 1)))\n"; @@ -158,15 +140,6 @@ HERE "" [(set_attr "type" "fused_load_cmpi") (set_attr "cost" "8") -HERE - - if ($lwa_insn) { - # prefixed_load_p needs the sign_extend attribute to validate lwa as a - # DS-form instruction instead of D-form. - print " (set_attr \"sign_extend\" \"yes\")\n"; - } - - print <<HERE (set_attr "length" "8")]) HERE diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 6b564837c6e..a16ee30f0c0 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1125,6 +1125,20 @@ return INTVAL (offset) % 4 == 0; }) +;; Return 1 if the operand is a memory operand that has a valid address for +;; a DS-form instruction. I.e. the address has to be either just a register, +;; or register + const where the two low order bits of const are zero. +(define_predicate "ds_form_mem_operand" + (match_code "subreg,mem") +{ + if (!any_memory_operand (op, mode)) + return false; + + rtx addr = XEXP (op, 0); + + return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS; +}) + ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. (define_predicate "symbol_ref_operand" (and (match_code "symbol_ref") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 75c5e5fc93d..b0db8ae508d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -287,7 +287,7 @@ ;; Whether this insn has a prefixed form and a non-prefixed form. (define_attr "maybe_prefixed" "no,yes" (if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore, - integer,add,fused_load_cmpi") + integer,add") (const_string "yes") (const_string "no"))) @@ -302,7 +302,7 @@ (eq_attr "maybe_prefixed" "no")) (const_string "no") - (eq_attr "type" "load,fpload,vecload,fused_load_cmpi") + (eq_attr "type" "load,fpload,vecload") (if_then_else (match_test "prefixed_load_p (insn)") (const_string "yes") (const_string "no")) diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C deleted file mode 100644 index d0e66a0b897..00000000000 --- a/gcc/testsuite/g++.target/powerpc/pr105325.C +++ /dev/null @@ -1,26 +0,0 @@ -/* { dg-do assemble } */ -/* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-require-effective-target powerpc_prefixed_addr } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */ - -/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair - instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion - load + compare -1/0/1 patterns did not handle the possibility that the load - might be prefixed. The -fstack-protector option is needed to show the - bug. */ - -struct Ath__array1D { - int _current; - int getCnt() { return _current; } -}; -struct extMeasure { - int _mapTable[10000]; - Ath__array1D _metRCTable; -}; -void measureRC() { - extMeasure m; - for (; m._metRCTable.getCnt();) - for (;;) - ; -} diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c index 3efbb34f2b4..526a026d874 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c @@ -54,14 +54,14 @@ TEST(uint8_t) TEST(int8_t) /* { dg-final { scan-assembler-times "lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 4 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 24 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 8 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_DI_CC_none" 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "ld_cmpdi_cr0_DI_clobber_CC_none" 4 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_DI_CCUNS_none" 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "ld_cmpldi_cr0_DI_clobber_CCUNS_none" 1 { target lp64 } } } */ /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */ /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */ /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */ -/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */ /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */ /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */ @@ -73,8 +73,6 @@ TEST(int8_t) /* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_SI_CC_none" 36 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */ /* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_SI_CCUNS_none" 0 { target ilp32 } } } */
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