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* [gcc r14-4654] Support 32/64-bit vectorization for conversion between _Float16 and integer/float.
@ 2023-10-16 1:08 hongtao Liu
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From: hongtao Liu @ 2023-10-16 1:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e6d063086726ccb2c5219611319285099a628878
commit r14-4654-ge6d063086726ccb2c5219611319285099a628878
Author: liuhongt <hongtao.liu@intel.com>
Date: Wed Oct 11 17:14:47 2023 +0800
Support 32/64-bit vectorization for conversion between _Float16 and integer/float.
gcc/ChangeLog:
* config/i386/mmx.md (V2FI_32): New mode iterator
(movd_v2hf_to_sse): Rename to ..
(movd_<mode>_to_sse): .. this.
(movd_v2hf_to_sse_reg): Rename to ..
(movd_<mode>_to_sse_reg): .. this.
(fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2): New
expander.
(fix<fixunssuffix>_truncv2hfv2si2): Ditto.
(float<floatunssuffix><mmxintvecmodelower><mode>2): Ditto.
(float<floatunssuffix>v2siv2hf2): Ditto.
(extendv2hfv2sf2): Ditto.
(truncv2sfv2hf2): Ditto.
* config/i386/sse.md (*vec_concatv8hf_movss): Rename to ..
(*vec_concat<mode>_movss): .. this.
gcc/testsuite/ChangeLog:
* gcc.target/i386/part-vect-hf-convert-1.c: New test.
Diff:
---
gcc/config/i386/mmx.md | 164 ++++++++++++++++++---
gcc/config/i386/sse.md | 12 +-
.../gcc.target/i386/part-vect-hf-convert-1.c | 111 ++++++++++++++
3 files changed, 262 insertions(+), 25 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 91674b4675e..82ca49c207b 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -60,6 +60,7 @@
;; All 4-byte integer/float16 vector modes
(define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF])
+(define_mode_iterator V2FI_32 [V2HF V2BF V2HI])
;; 4-byte integer vector modes
(define_mode_iterator VI_32 [V4QI V2HI])
@@ -79,7 +80,7 @@
;; V2S* modes
(define_mode_iterator V2FI [V2SF V2SI])
-(define_mode_iterator V2FI_V4HF [V2SF V2SI V4HF])
+(define_mode_iterator V24FI [V2SF V2SI V4HF V4HI])
;; Mapping from integer vector mode to mnemonic suffix
(define_mode_attr mmxvecsize
[(V8QI "b") (V4QI "b") (V2QI "b")
@@ -100,7 +101,7 @@
;; Mapping of vector float modes to an integer mode of the same size
(define_mode_attr mmxintvecmode
[(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
- (V4HF "V4HF") (V2HF "V2HI")])
+ (V4HF "V4HI") (V2HF "V2HI")])
(define_mode_attr mmxintvecmodelower
[(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")
@@ -108,7 +109,7 @@
;; Mapping of vector modes to a vector mode of double size
(define_mode_attr mmxdoublevecmode
- [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF")])
+ [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")])
;; Mapping of vector modes back to the scalar modes
(define_mode_attr mmxscalarmode
@@ -600,7 +601,7 @@
(define_expand "movq_<mode>_to_sse"
[(set (match_operand:<mmxdoublevecmode> 0 "register_operand")
(vec_concat:<mmxdoublevecmode>
- (match_operand:V2FI_V4HF 1 "nonimmediate_operand")
+ (match_operand:V24FI 1 "nonimmediate_operand")
(match_dup 2)))]
"TARGET_SSE2"
{
@@ -1967,31 +1968,40 @@
DONE;
})
-(define_mode_attr mov_to_sse_suffix [(V2HF "d") (V4HF "q")])
-(define_expand "movd_v2hf_to_sse"
- [(set (match_operand:V8HF 0 "register_operand")
- (vec_merge:V8HF
- (vec_duplicate:V8HF
- (match_operand:V2HF 1 "nonimmediate_operand"))
+(define_mode_attr mov_to_sse_suffix
+ [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")])
+
+(define_mode_attr mmxxmmmode
+ [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")])
+
+(define_mode_attr mmxxmmmodelower
+ [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")])
+
+(define_expand "movd_<mode>_to_sse"
+ [(set (match_operand:<mmxxmmmode> 0 "register_operand")
+ (vec_merge:<mmxxmmmode>
+ (vec_duplicate:<mmxxmmmode>
+ (match_operand:V2FI_32 1 "nonimmediate_operand"))
(match_dup 2)
(const_int 3)))]
"TARGET_SSE"
{
if (!flag_trapping_math)
{
- rtx op1 = force_reg (V2HFmode, operands[1]);
- emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode));
+ rtx op1 = force_reg (<MODE>mode, operands[1]);
+ emit_move_insn (operands[0],
+ lowpart_subreg (<mmxxmmmode>mode, op1, <MODE>mode));
DONE;
}
- operands[2] = CONST0_RTX (V8HFmode);
+ operands[2] = CONST0_RTX (<mmxxmmmode>mode);
})
-(define_expand "movd_v2hf_to_sse_reg"
- [(set (match_operand:V8HF 0 "register_operand")
- (vec_merge:V8HF
- (vec_duplicate:V8HF
- (match_operand:V2HF 1 "nonimmediate_operand"))
- (match_operand:V8HF 2 "register_operand")
+(define_expand "movd_<mode>_to_sse_reg"
+ [(set (match_operand:<mmxxmmmode> 0 "register_operand")
+ (vec_merge:<mmxxmmmode>
+ (vec_duplicate:<mmxxmmmode>
+ (match_operand:V2FI_32 1 "nonimmediate_operand"))
+ (match_operand:<mmxxmmmode> 2 "register_operand")
(const_int 3)))]
"TARGET_SSE")
@@ -2353,6 +2363,122 @@
"TARGET_SSE2"
"operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Parallel single-precision floating point conversion operations
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_expand "fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2"
+ [(set (match_operand:<mmxintvecmode> 0 "register_operand")
+ (any_fix:<mmxintvecmode>
+ (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V8HFmode);
+ rtx op0 = gen_reg_rtx (V8HImode);
+
+ emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
+
+ emit_insn (gen_fix<fixunssuffix>_truncv8hfv8hi2 (op0, op1));
+
+ emit_move_insn (operands[0],
+ lowpart_subreg (<mmxintvecmode>mode, op0, V8HImode));
+ DONE;
+})
+
+(define_expand "fix<fixunssuffix>_truncv2hfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand")
+ (any_fix:V2SI
+ (match_operand:V2HF 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL
+ && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V8HFmode);
+ rtx op0 = gen_reg_rtx (V4SImode);
+
+ emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
+
+ emit_insn (gen_avx512fp16_fix<fixunssuffix>_truncv4si2 (op0, op1));
+
+ emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
+ DONE;
+})
+
+(define_expand "float<floatunssuffix><mmxintvecmodelower><mode>2"
+ [(set (match_operand:VHF_32_64 0 "register_operand")
+ (any_float:VHF_32_64
+ (match_operand:<mmxintvecmode> 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V8HImode);
+ rtx op0 = gen_reg_rtx (V8HFmode);
+
+ rtx (*gen_movd_sse) (rtx, rtx)
+ = gen_mov<mov_to_sse_suffix>_<mmxintvecmodelower>_to_sse;
+ emit_insn (gen_movd_sse (op1, operands[1]));
+
+ emit_insn (gen_float<floatunssuffix>v8hiv8hf2 (op0, op1));
+
+ emit_move_insn (operands[0],
+ lowpart_subreg (<MODE>mode, op0, V8HFmode));
+ DONE;
+})
+
+(define_expand "float<floatunssuffix>v2siv2hf2"
+ [(set (match_operand:V2HF 0 "register_operand")
+ (any_float:V2HF
+ (match_operand:V2SI 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL
+ && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V4SImode);
+ rtx op0 = gen_reg_rtx (V8HFmode);
+
+ emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
+
+ emit_insn (gen_avx512fp16_float<floatunssuffix>v4siv4hf2 (op0, op1));
+
+ emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
+ DONE;
+})
+
+(define_expand "extendv2hfv2sf2"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (float_extend:V2SF
+ (match_operand:V2HF 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL
+ && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V8HFmode);
+ rtx op0 = gen_reg_rtx (V4SFmode);
+
+ emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
+
+ emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1));
+
+ emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
+ DONE;
+})
+
+(define_expand "truncv2sfv2hf2"
+ [(set (match_operand:V2HF 0 "register_operand")
+ (float_truncate:V2HF
+ (match_operand:V2SF 1 "nonimmediate_operand")))]
+ "TARGET_AVX512FP16 && TARGET_AVX512VL
+ && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
+{
+ rtx op1 = gen_reg_rtx (V4SFmode);
+ rtx op0 = gen_reg_rtx (V8HFmode);
+
+ emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
+
+ emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1));
+
+ emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
+ DONE;
+})
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel integral arithmetic
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9feb63716ef..c988935d4df 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11019,12 +11019,12 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DF")])
-(define_insn "*vec_concatv8hf_movss"
- [(set (match_operand:V8HF 0 "register_operand" "=x,v,v")
- (vec_merge:V8HF
- (vec_duplicate:V8HF
- (match_operand:V2HF 2 "nonimmediate_operand" "x,m,v"))
- (match_operand:V8HF 1 "reg_or_0_operand" "0,C,v" )
+(define_insn "*vec_concat<mmxxmmmodelower>_movss"
+ [(set (match_operand:<mmxxmmmode> 0 "register_operand" "=x,v,v")
+ (vec_merge:<mmxxmmmode>
+ (vec_duplicate:<mmxxmmmode>
+ (match_operand:V2FI_32 2 "nonimmediate_operand" "x,m,v"))
+ (match_operand:<mmxxmmmode> 1 "reg_or_0_operand" "0,C,v" )
(const_int 3)))]
"TARGET_SSE"
"@
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c
new file mode 100644
index 00000000000..95426015b58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/part-vect-hf-convert-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times {(?n)vcvttph2w[ \t]} 2 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvttph2uw[ \t]} 2 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvttph2dq[ \t]} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvttph2udq[ \t]} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtw2ph[ \t]} 2 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtuw2ph[ \t]} 2 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtdq2phx[ \t]} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtudq2phx[ \t]} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtph2psx[ \t]} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvtps2phxx[ \t]} 1 } } */
+
+
+void
+fix_32 (short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pa[i] = pb[i];
+}
+
+void
+fix_64 (short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 4; i++)
+ pa[i] = pb[i];
+}
+
+void
+fixuns_32 (unsigned short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pa[i] = pb[i];
+}
+
+void
+fixuns_64 (unsigned short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 4; i++)
+ pa[i] = pb[i];
+}
+
+void
+float_32 (short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pb[i] = pa[i];
+}
+
+void
+float_64 (short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 4; i++)
+ pb[i] = pa[i];
+}
+
+void
+floatuns_32 (unsigned short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pb[i] = pa[i];
+}
+
+void
+floatuns_64 (unsigned short* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 4; i++)
+ pb[i] = pa[i];
+}
+
+void
+fix_32si (int* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pa[i] = pb[i];
+}
+
+void
+fix_32usi (unsigned int* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pa[i] = pb[i];
+}
+
+void
+float_32si (int* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pb[i] = pa[i];
+}
+
+void
+float_32usi (unsigned int* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pb[i] = pa[i];
+}
+
+void
+float_extend (float* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pa[i] = pb[i];
+}
+
+void
+float_truncate (float* __restrict pa, _Float16* pb)
+{
+ for (int i = 0; i != 2; i++)
+ pb[i] = pa[i];
+}
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