[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:9e12217e60c7b20760b706937a512c5554d72f72

commit 9e12217e60c7b20760b706937a512c5554d72f72
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 16:46:25 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0075b9b4ee02..2af91a5ae2ae 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,69 @@
+==================== Branch work139, patch #3 ====================
+
+Power10: Add options to disable load and store vector pair.
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options.  The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair.  The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction.  The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The current default for -mcpu=power10 is that both load vector pair and store
+vector pair are enabled.
+
+I decided that if the user explicitly used the __builtin_vsx_lxvp or the
+__builtin_vsx_stxvp built-in functions to load or store a vector pair, that
+those functions would always generate a vector pair instruction.
+
+I added code so that the user code modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test.  There were no regressions in any
+of the tests, and the new tests passed.  Can I check this patch into the master
+branch?
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movoo): Add support for -mload-vector-pair and
+	-mstore-vector-pair.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Likewise.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.md (rs6000_setup_reg_addr_masks): If either load
+	vector pair or store vector pair instructions are not being generated,
+	don't allow lxvpx or stxvpx to be generated.
+	(rs6000_option_override_internal): Add warnings if either
+	-mload-vector-pair or -mstore-vector-pair is used without having MMA
+	instructions.
+	(rs6000_opt_masks): Allow user to override -mload-vector-pair or
+	-mstore-vector-pair via #pragma or attribute.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-pair-attribute.c: New test.
+	* gcc.target/powerpc/vector-pair-pragma.c: New test.
+	* gcc.target/powerpc/vector-pair-switch1.c: New test.
+	* gcc.target/powerpc/vector-pair-switch2.c: New test.
+	* gcc.target/powerpc/vector-pair-switch3.c: New test.
+	* gcc.target/powerpc/vector-pair-switch4.c: New test.
+
 ==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:b9fc9cab974ca52532fb4f3243159323c3791c07

commit b9fc9cab974ca52532fb4f3243159323c3791c07
Merge: 6583f68a903b c9aff00f391a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Oct 16 14:23:12 2023 -0400

    Update ChangeLog.meissner

Diff:

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:6583f68a903b344645f41569754fe33f606900fd

commit 6583f68a903b344645f41569754fe33f606900fd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 16:46:25 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8e8937d08cd2..12fb7862fe65 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,8 +1,4 @@
-<<<<<<< HEAD
 ==================== Branch work139, patch #3 ====================
-=======
-==================== Branch work139, patch #2 ====================
->>>>>>> c58761b70f6 (Update ChangeLog.meissner)
 
 Power10: Add options to disable load and store vector pair.
 
@@ -16,7 +12,6 @@ option would tell GCC to generate two load vector instructions instead of a
 single load vector pair.  The -mno-store-vector-pair option would tell GCC to
 generate two store vector instructions instead of a single store vector pair.
 
-<<<<<<< HEAD
 If either -mno-load-vector-pair is used, GCC will not generate the indexed
 stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
 generate the indexed lxvpx instruction.  The reason for this is to enable
@@ -29,17 +24,6 @@ vector pair are enabled.
 I decided that if the user explicitly used the __builtin_vsx_lxvp or the
 __builtin_vsx_stxvp built-in functions to load or store a vector pair, that
 those functions would always generate a vector pair instruction.
-=======
-| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
-| Author: Jiufu Guo <guojiufu@linux.ibm.com>
-| Date:   Tue Jan 10 20:52:33 2023 +0800
-|
-|   rs6000: build constant via li/lis;rldicl/rldicr
-|
-|   If a constant is possible left/right cleaned on a rotated value from
-|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
-|   to build the constant.
->>>>>>> c58761b70f6 (Update ChangeLog.meissner)
 
 I added code so that the user code modify these settings using either a
 '#pragma GCC target' directive or used __attribute__((__target__(...))) in the
@@ -80,9 +64,9 @@ gcc/testsuite/
 	* gcc.target/powerpc/vector-pair-switch3.c: New test.
 	* gcc.target/powerpc/vector-pair-switch4.c: New test.
 
-==================== Branch work139, patch #2 applied to trunk ====================
+==================== Branch work139, patch #2 was reverted ====================
 
-==================== Branch work139, patch #1 was reverted ====================
+==================== Branch work139, patch #1 was applied to the trunk ====================
 
 ==================== Branch work139, baseline ====================

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:3867e6aeda3a54c0cdc4b9bf7e80d7edadd174d9

commit 3867e6aeda3a54c0cdc4b9bf7e80d7edadd174d9
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:51:50 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 17fa7658723b..8e8937d08cd2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,8 @@
+<<<<<<< HEAD
 ==================== Branch work139, patch #3 ====================
+=======
+==================== Branch work139, patch #2 ====================
+>>>>>>> c58761b70f6 (Update ChangeLog.meissner)
 
 Power10: Add options to disable load and store vector pair.
 
@@ -12,6 +16,7 @@ option would tell GCC to generate two load vector instructions instead of a
 single load vector pair.  The -mno-store-vector-pair option would tell GCC to
 generate two store vector instructions instead of a single store vector pair.
 
+<<<<<<< HEAD
 If either -mno-load-vector-pair is used, GCC will not generate the indexed
 stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
 generate the indexed lxvpx instruction.  The reason for this is to enable
@@ -24,6 +29,17 @@ vector pair are enabled.
 I decided that if the user explicitly used the __builtin_vsx_lxvp or the
 __builtin_vsx_stxvp built-in functions to load or store a vector pair, that
 those functions would always generate a vector pair instruction.
+=======
+| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+| Author: Jiufu Guo <guojiufu@linux.ibm.com>
+| Date:   Tue Jan 10 20:52:33 2023 +0800
+|
+|   rs6000: build constant via li/lis;rldicl/rldicr
+|
+|   If a constant is possible left/right cleaned on a rotated value from
+|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+|   to build the constant.
+>>>>>>> c58761b70f6 (Update ChangeLog.meissner)
 
 I added code so that the user code modify these settings using either a
 '#pragma GCC target' directive or used __attribute__((__target__(...))) in the
@@ -66,6 +82,8 @@ gcc/testsuite/
 
 ==================== Branch work139, patch #2 applied to trunk ====================
 
+==================== Branch work139, patch #1 was reverted ====================
+
 ==================== Branch work139, baseline ====================
 
 Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:66c36aef032ce8876620f44c6ce23631e9011235

commit 66c36aef032ce8876620f44c6ce23631e9011235
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:10:00 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 45 +--------------------------------------------
 1 file changed, 1 insertion(+), 44 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 2f6352e33f00..17fa7658723b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -64,48 +64,7 @@ gcc/testsuite/
 	* gcc.target/powerpc/vector-pair-switch3.c: New test.
 	* gcc.target/powerpc/vector-pair-switch4.c: New test.
 
-==================== Branch work139, patch #2 ====================
-
-PowerPC: Do not depend on an undefined shift
-
-I was building a cross compiler to PowerPC on my x86_86 workstation with the
-latest version of GCC on October 11th.  I could not build the compiler on the
-x86_64 system as it died in building libgcc.  I looked into it, and I
-discovered the compiler was recursing until it ran out of stack space.  If I
-build a native compiler with the same sources on a PowerPC system, it builds
-fine.
-
-I traced this down to a change made around October 10th:
-
-| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
-| Author: Jiufu Guo <guojiufu@linux.ibm.com>
-| Date:   Tue Jan 10 20:52:33 2023 +0800
-|
-|   rs6000: build constant via li/lis;rldicl/rldicr
-|
-|   If a constant is possible left/right cleaned on a rotated value from
-|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
-|   to build the constant.
-
-The code was doing a -1 << 64 which is undefined behavior because different
-machines produce different results.  On the x86_64 system, (-1 << 64) produces
--1 while on a PowerPC 64-bit system, (-1 << 64) produces 0.  The x86_64 then
-recurses until the stack runs out of space.
-
-If I apply this patch, the compiler builds fine on both x86_64 as a PowerPC
-crosss compiler and on a native PowerPC system.
-
-2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-
-	PR target/111778
-	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
-	code from shifts that are undefined.
-	(can_be_built_by_li_lis_and_rldicr): Likewise.
-	(can_be_built_by_li_and_rldic): Likewise.
-
-==================== Branch work139, patch #1 was reverted ====================
+==================== Branch work139, patch #2 applied to trunk ====================
 
 ==================== Branch work139, baseline ====================
 
@@ -142,8 +101,6 @@ libgcc/
 
 	* ChangeLog.meissner: New file.
 
-==================== Branch work139, baseline ====================
-
 2023-10-11   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:388cde8912b2fa3b206758988b59d7c301bc2ed2

commit 388cde8912b2fa3b206758988b59d7c301bc2ed2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:51:50 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 5021e3ab1f2f..0075b9b4ee02 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work139, patch #1 ====================
+==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift
 
@@ -11,15 +11,15 @@ fine.
 
 I traced this down to a change made around October 10th:
 
-commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
-Author: Jiufu Guo <guojiufu@linux.ibm.com>
-Date:   Tue Jan 10 20:52:33 2023 +0800
-
-    rs6000: build constant via li/lis;rldicl/rldicr
-
-    If a constant is possible left/right cleaned on a rotated value from
-    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
-    to build the constant.
+| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+| Author: Jiufu Guo <guojiufu@linux.ibm.com>
+| Date:   Tue Jan 10 20:52:33 2023 +0800
+|
+|   rs6000: build constant via li/lis;rldicl/rldicr
+|
+|   If a constant is possible left/right cleaned on a rotated value from
+|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+|   to build the constant.
 
 The code was doing a -1 << 64 which is undefined behavior because different
 machines produce different results.  On the x86_64 system, (-1 << 64) produces
@@ -34,8 +34,12 @@ crosss compiler and on a native PowerPC system.
 gcc/
 
 	PR target/111778
-	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
-	use a shift left by the number of bits in a host wide int.
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
+	code from shifts that are undefined.
+	(can_be_built_by_li_lis_and_rldicr): Likewise.
+	(can_be_built_by_li_and_rldic): Likewise.
+
+==================== Branch work139, patch #1 was reverted ====================
 
 ==================== Branch work139, baseline ====================

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:39d18e7b7cb4e717065fbb2c4b705f11be848fe2

commit 39d18e7b7cb4e717065fbb2c4b705f11be848fe2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:10:00 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9f1909094939..5021e3ab1f2f 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,77 @@
+==================== Branch work139, patch #1 ====================
+
+PowerPC: Do not depend on an undefined shift
+
+I was building a cross compiler to PowerPC on my x86_86 workstation with the
+latest version of GCC on October 11th.  I could not build the compiler on the
+x86_64 system as it died in building libgcc.  I looked into it, and I
+discovered the compiler was recursing until it ran out of stack space.  If I
+build a native compiler with the same sources on a PowerPC system, it builds
+fine.
+
+I traced this down to a change made around October 10th:
+
+commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+Author: Jiufu Guo <guojiufu@linux.ibm.com>
+Date:   Tue Jan 10 20:52:33 2023 +0800
+
+    rs6000: build constant via li/lis;rldicl/rldicr
+
+    If a constant is possible left/right cleaned on a rotated value from
+    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+    to build the constant.
+
+The code was doing a -1 << 64 which is undefined behavior because different
+machines produce different results.  On the x86_64 system, (-1 << 64) produces
+-1 while on a PowerPC 64-bit system, (-1 << 64) produces 0.  The x86_64 then
+recurses until the stack runs out of space.
+
+If I apply this patch, the compiler builds fine on both x86_64 as a PowerPC
+crosss compiler and on a native PowerPC system.
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/111778
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
+	use a shift left by the number of bits in a host wide int.
+
 ==================== Branch work139, baseline ====================
 
+Add ChangeLog.meissner and REVISION.
+
+2023-10-11  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* REVISION: New file for branch.
+	* ChangeLog.meissner: New file.
+
+gcc/c-family/
+
+	* ChangeLog.meissner: New file.
+
+gcc/c/
+
+	* ChangeLog.meissner: New file.
+
+gcc/cp/
+
+	* ChangeLog.meissner: New file.
+
+gcc/fortran/
+
+	* ChangeLog.meissner: New file.
+
+gcc/testsuite/
+
+	* ChangeLog.meissner: New file.
+
+libgcc/
+
+	* ChangeLog.meissner: New file.
+
 2023-10-11   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:a6348eec1a65369f7c3adf1e7e31865742357a5b

commit a6348eec1a65369f7c3adf1e7e31865742357a5b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 16:46:25 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0075b9b4ee0..2af91a5ae2a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,69 @@
+==================== Branch work139, patch #3 ====================
+
+Power10: Add options to disable load and store vector pair.
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options.  The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair.  The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction.  The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The current default for -mcpu=power10 is that both load vector pair and store
+vector pair are enabled.
+
+I decided that if the user explicitly used the __builtin_vsx_lxvp or the
+__builtin_vsx_stxvp built-in functions to load or store a vector pair, that
+those functions would always generate a vector pair instruction.
+
+I added code so that the user code modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test.  There were no regressions in any
+of the tests, and the new tests passed.  Can I check this patch into the master
+branch?
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movoo): Add support for -mload-vector-pair and
+	-mstore-vector-pair.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Likewise.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.md (rs6000_setup_reg_addr_masks): If either load
+	vector pair or store vector pair instructions are not being generated,
+	don't allow lxvpx or stxvpx to be generated.
+	(rs6000_option_override_internal): Add warnings if either
+	-mload-vector-pair or -mstore-vector-pair is used without having MMA
+	instructions.
+	(rs6000_opt_masks): Allow user to override -mload-vector-pair or
+	-mstore-vector-pair via #pragma or attribute.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-pair-attribute.c: New test.
+	* gcc.target/powerpc/vector-pair-pragma.c: New test.
+	* gcc.target/powerpc/vector-pair-switch1.c: New test.
+	* gcc.target/powerpc/vector-pair-switch2.c: New test.
+	* gcc.target/powerpc/vector-pair-switch3.c: New test.
+	* gcc.target/powerpc/vector-pair-switch4.c: New test.
+
 ==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:448688aaf59f866c3dbd5c3d0e3c764147f37fb7

commit 448688aaf59f866c3dbd5c3d0e3c764147f37fb7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:51:50 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 5021e3ab1f2..0075b9b4ee0 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work139, patch #1 ====================
+==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift
 
@@ -11,15 +11,15 @@ fine.
 
 I traced this down to a change made around October 10th:
 
-commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
-Author: Jiufu Guo <guojiufu@linux.ibm.com>
-Date:   Tue Jan 10 20:52:33 2023 +0800
-
-    rs6000: build constant via li/lis;rldicl/rldicr
-
-    If a constant is possible left/right cleaned on a rotated value from
-    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
-    to build the constant.
+| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+| Author: Jiufu Guo <guojiufu@linux.ibm.com>
+| Date:   Tue Jan 10 20:52:33 2023 +0800
+|
+|   rs6000: build constant via li/lis;rldicl/rldicr
+|
+|   If a constant is possible left/right cleaned on a rotated value from
+|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+|   to build the constant.
 
 The code was doing a -1 << 64 which is undefined behavior because different
 machines produce different results.  On the x86_64 system, (-1 << 64) produces
@@ -34,8 +34,12 @@ crosss compiler and on a native PowerPC system.
 gcc/
 
 	PR target/111778
-	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
-	use a shift left by the number of bits in a host wide int.
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
+	code from shifts that are undefined.
+	(can_be_built_by_li_lis_and_rldicr): Likewise.
+	(can_be_built_by_li_and_rldic): Likewise.
+
+==================== Branch work139, patch #1 was reverted ====================
 
 ==================== Branch work139, baseline ====================

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:310c14a9e916faaf9cba3c0b7cc1bda299683730

commit 310c14a9e916faaf9cba3c0b7cc1bda299683730
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:10:00 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9f190909493..5021e3ab1f2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,77 @@
+==================== Branch work139, patch #1 ====================
+
+PowerPC: Do not depend on an undefined shift
+
+I was building a cross compiler to PowerPC on my x86_86 workstation with the
+latest version of GCC on October 11th.  I could not build the compiler on the
+x86_64 system as it died in building libgcc.  I looked into it, and I
+discovered the compiler was recursing until it ran out of stack space.  If I
+build a native compiler with the same sources on a PowerPC system, it builds
+fine.
+
+I traced this down to a change made around October 10th:
+
+commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+Author: Jiufu Guo <guojiufu@linux.ibm.com>
+Date:   Tue Jan 10 20:52:33 2023 +0800
+
+    rs6000: build constant via li/lis;rldicl/rldicr
+
+    If a constant is possible left/right cleaned on a rotated value from
+    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+    to build the constant.
+
+The code was doing a -1 << 64 which is undefined behavior because different
+machines produce different results.  On the x86_64 system, (-1 << 64) produces
+-1 while on a PowerPC 64-bit system, (-1 << 64) produces 0.  The x86_64 then
+recurses until the stack runs out of space.
+
+If I apply this patch, the compiler builds fine on both x86_64 as a PowerPC
+crosss compiler and on a native PowerPC system.
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/111778
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
+	use a shift left by the number of bits in a host wide int.
+
 ==================== Branch work139, baseline ====================
 
+Add ChangeLog.meissner and REVISION.
+
+2023-10-11  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* REVISION: New file for branch.
+	* ChangeLog.meissner: New file.
+
+gcc/c-family/
+
+	* ChangeLog.meissner: New file.
+
+gcc/c/
+
+	* ChangeLog.meissner: New file.
+
+gcc/cp/
+
+	* ChangeLog.meissner: New file.
+
+gcc/fortran/
+
+	* ChangeLog.meissner: New file.
+
+gcc/testsuite/
+
+	* ChangeLog.meissner: New file.
+
+libgcc/
+
+	* ChangeLog.meissner: New file.
+
 2023-10-11   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:fc28666ccd68576b9a43581c14da45cc407a318e

commit fc28666ccd68576b9a43581c14da45cc407a318e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 16:46:25 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0075b9b4ee0..2af91a5ae2a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,69 @@
+==================== Branch work139, patch #3 ====================
+
+Power10: Add options to disable load and store vector pair.
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options.  The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair.  The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction.  The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The current default for -mcpu=power10 is that both load vector pair and store
+vector pair are enabled.
+
+I decided that if the user explicitly used the __builtin_vsx_lxvp or the
+__builtin_vsx_stxvp built-in functions to load or store a vector pair, that
+those functions would always generate a vector pair instruction.
+
+I added code so that the user code modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test.  There were no regressions in any
+of the tests, and the new tests passed.  Can I check this patch into the master
+branch?
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movoo): Add support for -mload-vector-pair and
+	-mstore-vector-pair.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Likewise.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.md (rs6000_setup_reg_addr_masks): If either load
+	vector pair or store vector pair instructions are not being generated,
+	don't allow lxvpx or stxvpx to be generated.
+	(rs6000_option_override_internal): Add warnings if either
+	-mload-vector-pair or -mstore-vector-pair is used without having MMA
+	instructions.
+	(rs6000_opt_masks): Allow user to override -mload-vector-pair or
+	-mstore-vector-pair via #pragma or attribute.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-pair-attribute.c: New test.
+	* gcc.target/powerpc/vector-pair-pragma.c: New test.
+	* gcc.target/powerpc/vector-pair-switch1.c: New test.
+	* gcc.target/powerpc/vector-pair-switch2.c: New test.
+	* gcc.target/powerpc/vector-pair-switch3.c: New test.
+	* gcc.target/powerpc/vector-pair-switch4.c: New test.
+
 ==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:c58761b70f6c099618d9e9e601b93f972b1a67ba

commit c58761b70f6c099618d9e9e601b93f972b1a67ba
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:51:50 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 5021e3ab1f2..0075b9b4ee0 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,4 @@
-==================== Branch work139, patch #1 ====================
+==================== Branch work139, patch #2 ====================
 
 PowerPC: Do not depend on an undefined shift
 
@@ -11,15 +11,15 @@ fine.
 
 I traced this down to a change made around October 10th:
 
-commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
-Author: Jiufu Guo <guojiufu@linux.ibm.com>
-Date:   Tue Jan 10 20:52:33 2023 +0800
-
-    rs6000: build constant via li/lis;rldicl/rldicr
-
-    If a constant is possible left/right cleaned on a rotated value from
-    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
-    to build the constant.
+| commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+| Author: Jiufu Guo <guojiufu@linux.ibm.com>
+| Date:   Tue Jan 10 20:52:33 2023 +0800
+|
+|   rs6000: build constant via li/lis;rldicl/rldicr
+|
+|   If a constant is possible left/right cleaned on a rotated value from
+|   a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+|   to build the constant.
 
 The code was doing a -1 << 64 which is undefined behavior because different
 machines produce different results.  On the x86_64 system, (-1 << 64) produces
@@ -34,8 +34,12 @@ crosss compiler and on a native PowerPC system.
 gcc/
 
 	PR target/111778
-	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
-	use a shift left by the number of bits in a host wide int.
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Protect
+	code from shifts that are undefined.
+	(can_be_built_by_li_lis_and_rldicr): Likewise.
+	(can_be_built_by_li_and_rldic): Likewise.
+
+==================== Branch work139, patch #1 was reverted ====================
 
 ==================== Branch work139, baseline ====================

[gcc(refs/users/meissner/heads/work139)] Update ChangeLog.meissner

[Michael Meissner]

https://gcc.gnu.org/g:de64b2ea8482fdeb55fc7e94162332ed2981fbc9

commit de64b2ea8482fdeb55fc7e94162332ed2981fbc9
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Oct 12 00:10:00 2023 -0400

    Update ChangeLog.meissner

Diff:
---
 gcc/ChangeLog.meissner | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9f190909493..5021e3ab1f2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,77 @@
+==================== Branch work139, patch #1 ====================
+
+PowerPC: Do not depend on an undefined shift
+
+I was building a cross compiler to PowerPC on my x86_86 workstation with the
+latest version of GCC on October 11th.  I could not build the compiler on the
+x86_64 system as it died in building libgcc.  I looked into it, and I
+discovered the compiler was recursing until it ran out of stack space.  If I
+build a native compiler with the same sources on a PowerPC system, it builds
+fine.
+
+I traced this down to a change made around October 10th:
+
+commit 8f1a70a4fbcc6441c70da60d4ef6db1e5635e18a (HEAD)
+Author: Jiufu Guo <guojiufu@linux.ibm.com>
+Date:   Tue Jan 10 20:52:33 2023 +0800
+
+    rs6000: build constant via li/lis;rldicl/rldicr
+
+    If a constant is possible left/right cleaned on a rotated value from
+    a negative value of "li/lis".  Then, using "li/lis ; rldicl/rldicr"
+    to build the constant.
+
+The code was doing a -1 << 64 which is undefined behavior because different
+machines produce different results.  On the x86_64 system, (-1 << 64) produces
+-1 while on a PowerPC 64-bit system, (-1 << 64) produces 0.  The x86_64 then
+recurses until the stack runs out of space.
+
+If I apply this patch, the compiler builds fine on both x86_64 as a PowerPC
+crosss compiler and on a native PowerPC system.
+
+2023-10-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/111778
+	* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): Do not
+	use a shift left by the number of bits in a host wide int.
+
 ==================== Branch work139, baseline ====================
 
+Add ChangeLog.meissner and REVISION.
+
+2023-10-11  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* REVISION: New file for branch.
+	* ChangeLog.meissner: New file.
+
+gcc/c-family/
+
+	* ChangeLog.meissner: New file.
+
+gcc/c/
+
+	* ChangeLog.meissner: New file.
+
+gcc/cp/
+
+	* ChangeLog.meissner: New file.
+
+gcc/fortran/
+
+	* ChangeLog.meissner: New file.
+
+gcc/testsuite/
+
+	* ChangeLog.meissner: New file.
+
+libgcc/
+
+	* ChangeLog.meissner: New file.
+
 2023-10-11   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch