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* [gcc(refs/vendors/vrull/heads/slp-improvements)] Add testcase for #344
@ 2024-01-23 20:58 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2024-01-23 20:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:be077bfec2c9d3beec3cd51f1912a27cb7c7ab63
commit be077bfec2c9d3beec3cd51f1912a27cb7c7ab63
Author: Manolis Tsamis <manolis.tsamis@vrull.eu>
Date: Tue Nov 28 15:31:17 2023 +0100
Add testcase for #344
Diff:
---
gcc/testsuite/gcc.target/aarch64/vins_uzp.c | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/vins_uzp.c b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
new file mode 100644
index 00000000000..d82d1f43c15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+typedef int v4si __attribute__ ((vector_size (4 * sizeof (int))));
+
+v4si case1(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 5, 0, 5);
+}
+
+v4si case2(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 5, 1, 5);
+}
+
+v4si case3(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 6, 0, 6);
+}
+
+v4si case4(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 7, 1, 7);
+}
+
+v4si case5(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 2, 7, 2, 7);
+}
+
+v4si case6(v4si a, v4si b) {
+ return __builtin_shufflevector (b, a, 2, 7, 2, 7);
+}
+
+v4si case7(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 7, 2, 7, 2);
+}
+
+/* { dg-final { scan-assembler-not {\ttbl\t} } } */
+/* { dg-final { scan-assembler-not {\tldr\t} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/vrull/heads/slp-improvements)] Add testcase for #344
@ 2024-01-17 19:14 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2024-01-17 19:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d485750f65c85aa2af916824e1fd434bc360d095
commit d485750f65c85aa2af916824e1fd434bc360d095
Author: Manolis Tsamis <manolis.tsamis@vrull.eu>
Date: Tue Nov 28 15:31:17 2023 +0100
Add testcase for #344
Diff:
---
gcc/testsuite/gcc.target/aarch64/vins_uzp.c | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/vins_uzp.c b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
new file mode 100644
index 00000000000..d82d1f43c15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+typedef int v4si __attribute__ ((vector_size (4 * sizeof (int))));
+
+v4si case1(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 5, 0, 5);
+}
+
+v4si case2(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 5, 1, 5);
+}
+
+v4si case3(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 6, 0, 6);
+}
+
+v4si case4(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 7, 1, 7);
+}
+
+v4si case5(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 2, 7, 2, 7);
+}
+
+v4si case6(v4si a, v4si b) {
+ return __builtin_shufflevector (b, a, 2, 7, 2, 7);
+}
+
+v4si case7(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 7, 2, 7, 2);
+}
+
+/* { dg-final { scan-assembler-not {\ttbl\t} } } */
+/* { dg-final { scan-assembler-not {\tldr\t} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/vendors/vrull/heads/slp-improvements)] Add testcase for #344
@ 2023-11-28 14:54 Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2023-11-28 14:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9326289ede1068d92c0d003fcd3737ab793ebfbd
commit 9326289ede1068d92c0d003fcd3737ab793ebfbd
Author: Manolis Tsamis <manolis.tsamis@vrull.eu>
Date: Tue Nov 28 15:31:17 2023 +0100
Add testcase for #344
Diff:
---
gcc/testsuite/gcc.target/aarch64/vins_uzp.c | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/vins_uzp.c b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
new file mode 100644
index 00000000000..d82d1f43c15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vins_uzp.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+typedef int v4si __attribute__ ((vector_size (4 * sizeof (int))));
+
+v4si case1(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 5, 0, 5);
+}
+
+v4si case2(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 5, 1, 5);
+}
+
+v4si case3(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 0, 6, 0, 6);
+}
+
+v4si case4(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 1, 7, 1, 7);
+}
+
+v4si case5(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 2, 7, 2, 7);
+}
+
+v4si case6(v4si a, v4si b) {
+ return __builtin_shufflevector (b, a, 2, 7, 2, 7);
+}
+
+v4si case7(v4si a, v4si b) {
+ return __builtin_shufflevector (a, b, 7, 2, 7, 2);
+}
+
+/* { dg-final { scan-assembler-not {\ttbl\t} } } */
+/* { dg-final { scan-assembler-not {\tldr\t} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
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