[gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:f678bb81d9bffa8896d3fb4714d7a226fe79464c

commit f678bb81d9bffa8896d3fb4714d7a226fe79464c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Feb 15 21:01:59 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.pnext | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext
index bd71535fe571..abff7b348e4f 100644
--- a/gcc/ChangeLog.pnext
+++ b/gcc/ChangeLog.pnext
@@ -1,5 +1,27 @@
 ==================== Branch work158-pnext, patch #201 ====================
 
+Add power11 aux vector and tests.
+
+2024-02-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/driver-rs6000.c (asm_names): Add power11 support.
+	* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Remove comment saying
+	this is not yet official.
+	(PPC_PLATFORM_POWER11): Add power11 support.
+	* config/rs6000/rs6000-builtin.cc (cpu_is_info): Likewise.
+
+gcc/testsuite/
+
+	* lib/target-support.exp (check_effective_target_power11_ok): Add
+	power11 support.
+	* gcc.target/powerpc/power11-1.c: New test.
+	* gcc.target/powerpc/power11-2.c: Likewise.
+	* gcc.target/powerpc/power11-3.c: Likewise.
+
+==================== Branch work158-pnext, patch #201 ====================
+
 Add -mcpu=power11 and -mcpu=future support.
 
 2024-02-15  Michael Meissner  <meissner@linux.ibm.com>

[gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:da458087c71a3ce1c0e9f5d114fc9420a70469c7

commit da458087c71a3ce1c0e9f5d114fc9420a70469c7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Feb 15 19:27:03 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.pnext | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext
index 68de3ce18c85..bd71535fe571 100644
--- a/gcc/ChangeLog.pnext
+++ b/gcc/ChangeLog.pnext
@@ -1,3 +1,35 @@
+==================== Branch work158-pnext, patch #201 ====================
+
+Add -mcpu=power11 and -mcpu=future support.
+
+2024-02-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Add support for power11 and
+	future processors.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR11 if -mcpu=power11 and _ARCH_PWR_FUTURE if -mcpu=future.
+	* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): Add support
+	for -mcpu=power11.
+	(ISA_FUTURE_MASKS_SERVER): Add support for -mcpu=future.
+	(POWERPC_MASKS): Add support for -mcpu=power11 and -mcpu=future.
+	(power11 cpu): Add power11 cpu.
+	(future cpu): Add future cpu.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro.
+	(PROCESSOR_FUTURE): Likewise.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11,
+	emit .machine power11.  If -mcpu=future emit .machine future.
+	(rs6000_opt_masks): Add support for power11 and future ISA bits.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
+	if -mcpu=future.  Pass -mpower11 to the assembler if -mcpu=power11.
+	* config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for
+	power11 cpu.
+	(-mfuture): New internal ISA bit for future cpu.
+	* doc/invoke.texi (PowerPC options): Document -mcpu=future and
+	-mcpu=power11.
+
 ==================== Branch work158-pnext, patch #200 was reverted ====================
 
 ==================== Branch work158-pnext, patches #111-116 were reverted ====================

[gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:6526329c046dc37a2c592d7ba12f775300f2b361

commit 6526329c046dc37a2c592d7ba12f775300f2b361
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Feb 15 18:45:14 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.pnext | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext
index 35c9601b022b..422782f69f96 100644
--- a/gcc/ChangeLog.pnext
+++ b/gcc/ChangeLog.pnext
@@ -1,3 +1,29 @@
+==================== Branch work158-pnext, patch #200 ====================
+
+Add -mcpu=power11 support.
+
+2024-02-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (powerpc*-*-*, rs6000-*-*): Add support for
+	--with-cpu=power11.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR11 if -mcpu=power11.
+	* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New macro.
+	(POWERPC_MASKS): Add -mcpu=power11 ISA bit.
+	(power11 cpu): New cpu target.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Define as
+	PROCESSOR_POWER10 for now.
+	* config/rs6000/rs6000-tables.optL: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Set .machine
+	power11 if -mcpu=power11.
+	(rs6000_opt_masks): Add Power11.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mpower11 to the assembler
+	if -mcpu=power11.
+	* config/rs6000/rs6000.opt (-mpower11): Add ISA bit for power11.
+	* doc/invoke.texi (PowerPC options): Document -mcpu=power11.
+
 ==================== Branch work158-pnext, patch #116 from work158-future branch ====================
 
 Add configure support for PowerPC future.

[gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:48a4b5c7b4c0cca39c0ffe21192d4c2d1ec74a99

commit 48a4b5c7b4c0cca39c0ffe21192d4c2d1ec74a99
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Feb 14 18:36:55 2024 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.pnext | 266 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 266 insertions(+)

diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext
index 307f509e053c..b8ec896e9b93 100644
--- a/gcc/ChangeLog.pnext
+++ b/gcc/ChangeLog.pnext
@@ -1,5 +1,271 @@
+==================== Branch work158-pnext, patch #107 from work158-future branch ====================
+
+Enable using vector pair load/store for -mcpu=future
+
+Late in the development of power10, we discovered that there were some issues
+in using load vector pair and store vector pair instructions to do memory
+copies, so the defaults were modified to not use these instructions.  This
+patch re-enables using load and store vector pair instructions.
+
+Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS.
+This means the option was not reset if the cpu was changed via target
+attributes or targt pragmas.  I added this mask to POWERPC_MASKS since the
+option is set via -mcpu=future.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Turn on
+	-mblock-ops-vector-pair for -mcpu=future.
+	(POWERPC_MASKS): Add -mblock-ops-vector-pair.
+
+==================== Branch work158-pnext, patch #106 from work158-future branch ====================
+
+Set future machine type in assembler if -mcpu=future
+
+This patch uses the .machine directive to tell the assembler to use any
+possible future instructions.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine
+	future if -mcpu=future.
+
+==================== Branch work158-pnext, patch #105 from work158-future branch ====================
+
+Make -mtune=future be the same as -mtune=power10.
+
+This patch makes -mcpu=future act like -mcpu=power10 in terms of tuning.  If
+future patches changes the tuning, then this patch woucl be changed to use the
+new tuning information.  Until there is different tuning, this patch does not
+allow the user to explicitly use -mtune=future.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
+	-mtune=future become -mtune=power10.
+
+==================== Branch work158-pnext, patch #104 from work158-future branch ====================
+
+Pass -mfuture to assembler if -mcpu=future.
+
+This patch passes -mfuture to the assembler if the user used -mcpu=future.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture
+	to the assembler.
+
+==================== Branch work158-pnext, patch #103 from work158-future branch ====================
+
+Define _ARCH_PWR_FUTURE if -mcpu=future.
+
+This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR_FUTURE if -mcpu=future.
+
+==================== Branch work158-pnext, patch #102 from work158-future branch ====================
+
+Add debugging for -mcpu=future
+
+This patch prints that -mcpu=future was selected if you use the debugging
+switch -mdebug=reg.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_opt_masks): Add entry to print out
+	-mfuture in the isa flags.
+
+==================== Branch work158-pnext, patch #101 from work158-future branch ====================
+
+Add initial -mcpu=future support.
+
+This patch adds the basic support for -mcpu=future, which is a framework to add
+support for possible future PowerPCs.  This patch is only sets the future bit
+in the ISA options.
+
+2024-02-14  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option
+	bits for -mcpu=future.
+	(POWERPC_MASKS): Add -mfuture mask.
+	(future cpu): Add -mcpu=future.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor type.
+	* config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Likewise.
+	* config/rs6000/rs6000.opt (-mfuture): New insert mask for -mcpu=future.
+	* doc/invoke.texi (PowerPC options): Add -mcpu=future.
+
+==================== Branch work158-pnext, patch #2 from work158 branch ====================
+
+PR target/112886, Add %S<n> to print_operand for vector pair support.
+
+In looking at support for load vector pair and store vector pair for the
+PowerPC in GCC, I noticed that we were missing a print_operand output modifier
+if you are dealing with vector pairs to print the 2nd register in the vector
+pair.
+
+If the instruction inside of the asm used the Altivec encoding, then we could
+use the %L<n> modifier:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2"
+		 : "=v" (*p)
+		 : "v" (*q), "v" (*r));
+
+Likewise if we know the value to be in a tradiational FPR register, %L<n> will
+work for instructions that use the VSX encoding:
+
+	__vector_pair *p, *q, *r;
+	// ...
+	__asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2"
+		 : "=f" (*p)
+		 : "f" (*q), "f" (*r));
+
+But if have a value that is in a traditional Altivec register, and the
+instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it
+should give a value between 32 and 63.
+
+This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the
+register number.
+
+This is version 2 of the patch.  The only difference is I made the test case
+simpler to read.
+
+I have tested this on power10 and power9 little endian systems and on a power9
+big endian system.  There were no regressions in the patch.  Can I apply it to
+the trunk?
+
+It would be nice if I could apply it to the open branches.  Can I backport it
+after a burn-in period?
+
+2024-02-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/112886
+	* config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier.
+	* doc/md.texi (Modifiers): Mention %S can be used like %x.
+
+gcc/testsuite/
+
+	PR target/112886
+	* /gcc.target/powerpc/pr112886.c: New test.
+
+==================== Branch work158-pnext, patch #1 from work158 branch ====================
+
+Power10: Add options to disable load and store vector pair.
+
+This is version 2 of the patch to add -mno-load-vector-pair and
+-mno-store-vector-pair undocumented tuning switches.
+
+The differences between the first version of the patch and this version is that
+I added explicit RTL abi attributes for when the compiler can generate the load
+vector pair and store vector pair instructions.  By having this attribute, the
+movoo insn has separate alternatives for when we generate the instruction and
+when we want to split the instruction into 2 separate vector loads or stores.
+
+In the first version of the patch, I had previously provided built-in functions
+that would always generate load vector pair and store vector pair instructions
+even if these instructions are normally disabled.  I found these built-ins
+weren't specified like the other vector pair built-ins, and I didn't include
+documentation for the built-in functions.  If we want such built-in functions,
+we can add them as a separate patch later.
+
+In addition, since both versions of the patch adds #pragma target and attribute
+support to change the results for individual functions, we can select on a
+function by function basis what the defaults for load/store vector pair is.
+
+The original text for the patch is:
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options.  The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair.  The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction.  The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The default for -mcpu=power10 is that both load vector pair and store vector
+pair are enabled.
+
+I added code so that the user code can modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test.  There were no regressions in any
+of the tests, and the new tests passed.  Can I check this patch into the master
+branch?
+
+2024-02-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and
+	-mno-store-vector-pair.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
+	-mload-vector-pair and -mstore-vector-pair.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow
+	indexed mode for OOmode if we are generating both load vector pair and
+	store vector pair instructions.
+	(rs6000_option_override_internal): Add support for -mno-load-vector-pair
+	and -mno-store-vector-pair.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp
+	attributes.
+	(enabled attribute): Likewise.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-pair-attribute.c: New test.
+	* gcc.target/powerpc/vector-pair-pragma.c: New test.
+	* gcc.target/powerpc/vector-pair-switch1.c: New test.
+	* gcc.target/powerpc/vector-pair-switch2.c: New test.
+	* gcc.target/powerpc/vector-pair-switch3.c: New test.
+	* gcc.target/powerpc/vector-pair-switch4.c: New test.
+
 ==================== Branch work158-pnext, baseline ====================
 
+Add ChangeLog.pnext and update REVISION.
+
+2024-02-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* ChangeLog.pnext: New file for branch.
+	* REVISION: Update.
+
 2024-02-09   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch