[gcc(refs/users/meissner/heads/work164-test)] Add -mmfspr option.

[gcc(refs/users/meissner/heads/work164-test)] Add -mmfspr option.

[Michael Meissner]

https://gcc.gnu.org/g:cdcfeb5aa467d17024891bdbc218531151b0f1d6

commit cdcfeb5aa467d17024891bdbc218531151b0f1d6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 25 20:24:59 2024 -0400

    Add -mmfspr option.
    
    2024-04-25  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-cpus.def (ISA_MASKS_2_7_SERVER): Add -mmfspr.
            (POWERPC_MASKS): Likewise.
            * config/rs6000/rs6000.cc (rs6000_register_move_cost): Check -mmfspr.
            * config/rs6000/rs6000.opt (-mmfspr): New option.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def | 2 ++
 gcc/config/rs6000/rs6000.cc       | 3 ++-
 gcc/config/rs6000/rs6000.opt      | 4 ++++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 7ea3ce09c8d..ecb9471d84a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -51,6 +51,7 @@
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DIRECT_MOVE		\
 				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
+				 | OPTION_MASK_MFSPR			\
 				 | OPTION_MASK_QUAD_MEMORY		\
 				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
 				 | OPTION_MASK_TAR)
@@ -138,6 +139,7 @@
 				 | OPTION_MASK_HTM			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MFCRF			\
+				 | OPTION_MASK_MFSPR			\
 				 | OPTION_MASK_MMA			\
 				 | OPTION_MASK_MODULO			\
 				 | OPTION_MASK_MULHW			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e5ebbd58cc0..4df4259335b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -22816,7 +22816,8 @@ rs6000_register_move_cost (machine_mode mode,
   /* Make moves from SPR registers (LR, CTR, TAR) more expensive so that the
      register allocator does not think of these registers are useful for saving
      results.  */
-  else if (reg_classes_intersect_p (from, SPECIAL_REGS)
+  else if (TARGET_MFSPR
+	   && reg_classes_intersect_p (from, SPECIAL_REGS)
 	   && reg_classes_intersect_p (to, GENERAL_REGS))
     {
       rclass = from;
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 8e9215a32c2..2cbf7c1db1c 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -607,6 +607,10 @@ mtar
 Target Mask(TAR) Var(rs6000_isa_flags)
 Generate (do not generate) code using the TAR register.
 
+mmfspr
+Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
+Generate (do not generate) code making move from SPR register expensive.
+
 mrelative-jumptables
 Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save