[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:19d46f68bba26bc9b3e0b15f6aa6326d653d0940

commit 19d46f68bba26bc9b3e0b15f6aa6326d653d0940
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 25 20:26:28 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 55cdbe9e14a..d30a9e2fbc6 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,16 @@
+==================== Branch work164-test, patch #306 ====================
+
+Add -mmfspr option.
+
+2024-04-25  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-cpus.def (ISA_MASKS_2_7_SERVER): Add -mmfspr.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_register_move_cost): Check -mmfspr.
+	* config/rs6000/rs6000.opt (-mmfspr): New option.
+
 ==================== Branch work164-test, patch #305 ====================
 
 Make moves from SPRs higher in cost.

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:d2805b66b9547d41e9fb3ee4c1ae2ecbbcd9077c

commit d2805b66b9547d41e9fb3ee4c1ae2ecbbcd9077c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Apr 25 18:12:15 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 146d70fca7f..55cdbe9e14a 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,14 @@
+==================== Branch work164-test, patch #305 ====================
+
+Make moves from SPRs higher in cost.
+
+2024-04-25  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_register_move_cost): Make moves from
+	SPRs more expensive.
+
 ==================== Branch work164-test, patch #304 ====================
 
 Adjust tests for tar register

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:df331a2f871bed812082295bb7afaa3ddd81ea60

commit df331a2f871bed812082295bb7afaa3ddd81ea60
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 15 18:38:39 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index fd5e9d14a39..146d70fca7f 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,16 @@
+==================== Branch work164-test, patch #304 ====================
+
+Adjust tests for tar register
+
+2024-04-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* gcc.target/powerpc/ppc-switch-1.c: Adjust test to account for using
+	the TAR regisgter.
+	* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+	* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+
 ==================== Branch work164-test, patch #303 ====================
 
 Update TAR support.

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:4b2a63df76b9046fd770e2748e9bd281c3becff1

commit 4b2a63df76b9046fd770e2748e9bd281c3becff1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 15 16:46:05 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 8b12e86f37b..fd5e9d14a39 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,28 @@
+==================== Branch work164-test, patch #303 ====================
+
+Update TAR support.
+
+2024-04-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Correctly print TAR
+	register.
+	(rs6000_init_hard_regno_mode_ok): Correctly initial TAR register.
+	* config/rs6000/rs6000.md (mov<mode>_internal): Add support for TAR
+	register.
+	(movcc_<mode>): Likewise.
+	(movsf_hardfloat): Likewise.
+	(movsf_hardfloat): Likewise.
+	(movsd_hardfloat): Likewise.
+	(mov<mode>_hardfloat64): Likewise.
+	(mov<mode>_softfloat6): Likewise.
+	(indirect_jump): Likewise.
+	(@indirect_jump<mode>_nospec): Likewise.
+	(<bd>tf_<mode>): Remove TAR register.
+	* lra-constraints.cc (lra_constraints): Add debug_rtx before raising an
+	error.
+
 ==================== Branch work164-test, patch #302 ====================
 
 Remove moves for tar register.

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:f8aff8ceb76e648416011419087304701c6e8911

commit f8aff8ceb76e648416011419087304701c6e8911
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 12 22:48:06 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index fcdb9e19c32..8b12e86f37b 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,19 @@
+==================== Branch work164-test, patch #302 ====================
+
+Remove moves for tar register.
+
+2024-04-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.md (movcc_<mode>): Remove tar register moves.
+	(movsf_hardfloa): Likewise.
+	(movsd_hardfloa): Likewise.
+	(mov<mode>_hardfloat64): Likewise.
+	(mov<mode>_softfloat6): Likewise.
+	(<bd>_<mode>): Likewise.
+	(<bd>tf_<mode>): Likewise.
+
 ==================== Branch work164-test, patch #301 ====================
 
 Update debug register number for the tar register.

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:cc0ccb073996f9df58b7390b24478bc229ecfca7

commit cc0ccb073996f9df58b7390b24478bc229ecfca7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 12 19:32:34 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 5ebe8ec4286..fcdb9e19c32 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,14 @@
+==================== Branch work164-test, patch #301 ====================
+
+Update debug register number for the tar register.
+
+2024-04-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_debugger_regno): Fix tar register
+	number.
+
 ==================== Branch work164-test, patch #300 ====================
 
 Add support for -mtar

[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*

[Michael Meissner]

https://gcc.gnu.org/g:9cf198d403a5281fb999be669b79f5914594c233

commit 9cf198d403a5281fb999be669b79f5914594c233
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 12 19:08:08 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 195 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 194 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 8ee53e57958..5ebe8ec4286 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,6 +1,199 @@
+==================== Branch work164-test, patch #300 ====================
+
+Add support for -mtar
+
+2024-04-12  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/constraints.md (h constraint): Add tar register to
+	documentation.
+	(wt constraint): New constraint.
+	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
+	(alt_reg_names): Likewise.
+	(rs6000_debug_reg_global): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Likewise.
+	(rs6000_option_override_internal): Likewise.
+	(rs6000_conditional_register_usage): Likewise.
+	(print_operand): Likewise.
+	(rs6000_debugger_regno): Likewise.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
+	(FiXED_REGISTERS): Likewise.
+	(CALL_REALLY_USED_REGISTERS): Likewise.
+	(REG_ALLOC_ORDER): Likewise.
+	(reg_class): Add new TAR_REGS register class.
+	(REG_CLASS_NAMES): Likewise.
+	(REG_CLASS_CONTENTS): Likewise.
+	(r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
+	(REG_NAMES): Add tar register.
+	* config/rs6000/rs6000.md (TAR_REGNO): New constant.
+	(movcc_<mode>): Add support for tar register.
+	(movsf_hardfloat): Likewise.
+	(movsf_hardfloat): Likewise.
+	(mov<mode>_softfloat): Likewise.
+	(mov<mode>_hardfloat64): Likewise.
+	(mov<mode>_softfloat6): Likewise.
+	(indirect_jump): Likewise.
+	(@indirect_jump<mode>_nospec): Likewise.
+	(@tablejump<mode>_absolute): Likewise.
+	(@tablejump<mode>_insn_nospec): Likewise.
+	(<bd>_<mode>): Likewise.
+	(<bd>tf_<mode>): Likewise.
+	* config/rs6000/rs6000.opt (-mtar): New option.
+	* doc/invoke.texi (RS/6000 options): Document -mtar.
+
+==================== Branch work164-test, patch #10 from work164 ====================
+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR_FUTURE if -mcpu=future.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+	(POWERPC_MASKS): Add future isa bit.
+	(power11 cpu): Add future definition.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+	* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+	support.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_reassociation_width): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Add future.
+	* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+	* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
+==================== Branch work164-test, patch #3 from work164 ====================
+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support.  In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/power11-1.c: New test.
+	* gcc.target/powerpc/power11-2.c: Likewise.
+	* gcc.target/powerpc/power11-3.c: Likewise.
+	* lib/target-supports.exp (check_effective_target_power11_ok): Add new
+	effective target.
+
+==================== Branch work164-test, patch #2 from work164 ====================
+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/power10.md (all reservations): Add power11 as an
+	alternative to power10.
+
+==================== Branch work164-test, patch #1 from work164 ====================
+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
+
+This patch adds support for using "power11" in the __builtin_cpu_is built-in
+function.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+	* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+	* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
+	* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	_ARCH_PWR11 if -mcpu=power11.
+	* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
+	(POWERPC_MASKS): Add power11 isa bit.
+	(power11 cpu): Add power11 definition.
+	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
+	* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
+	support.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_reassociation_width): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Add power11.
+	* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
+	* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
+
 ==================== Branch work164-test, baseline ====================
 
+Add ChangeLog.test and update REVISION.
+
+2024-04-08  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* ChangeLog.test: New file for branch.
+	* REVISION: Update.
+
 2024-04-08   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
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