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[gcc r13-4160] c++: implement P1492 contracts
2022-11-19 2:44 UTC
[gcc r13-4159] libstdc++: add experimental Contracts support
2022-11-19 2:44 UTC
[gcc r13-4158] analyzer: fix feasibility false +ve on jumps through function ptrs [PR107582]
2022-11-19 0:39 UTC
[gcc/devel/rust/master] Merge #1636
2022-11-18 23:34 UTC
[gcc/devel/rust/master] Merge #1652
2022-11-18 23:34 UTC
[gcc/devel/rust/master] Remove default location. Add visibility location to create_* functions
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump no comma after self in fn params if it is the last one
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump remove /* stmp */ comment to not clutter the dump
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Remove unused include in rust-ast-dump.cc
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump generic parameters
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump type param type
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump trait object type one bound
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump parenthesised type
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump trait object type
2022-11-18 23:34 UTC
[gcc/devel/rust/master] ast: Dump impl trait type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump impl trait type one bound
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump bare function type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump inferred type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump tuple type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump never type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump raw pointer type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump array type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] ast: Dump slice type
2022-11-18 23:33 UTC
[gcc/devel/rust/master] clang-format
2022-11-18 23:33 UTC
[gcc/devel/rust/master] add Location to AST::Visibility
2022-11-18 23:33 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] Add new flag 'falign-arrays'
2022-11-18 23:19 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Add support for str(n)cmp inline expansion
2022-11-18 23:19 UTC
[gcc r13-4157] analyzer: move more impl_* to known_function
2022-11-18 22:01 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Add support for strlen inline expansion
2022-11-18 20:27 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Use by-pieces to do overlapping accesses in block_move_straight
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Move riscv_block_move_loop to separate file
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Enable overlap-by-pieces via tune param
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use .p2align for code-alignment
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcvt: add if-conversion to conditional-zero instructions
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support immediates in XVentanaCondOps
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add instruction fusion (for ventana-vt1)
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add basic support for the Ventana-VT1 core
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion
2022-11-18 20:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Replace zero_extendsidi2_shifted with generalized split
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: fold two bit tests with different polarity
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: recognize single bit test of sign-bit
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimise adding a (larger than simm12) constant to a register
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero
2022-11-18 20:25 UTC
[gcc/vrull/heads/for-upstream] (23 commits) riscv: Add support for strlen inline expansion
2022-11-18 20:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Add support for strlen inline expansion
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Use by-pieces to do overlapping accesses in block_move_straight
2022-11-18 20:23 UTC
[gcc r13-4156] RISC-V: No extensions for SImode min/max against safe constant
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Move riscv_block_move_loop to separate file
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Enable overlap-by-pieces via tune param
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use .p2align for code-alignment
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcvt: add if-conversion to conditional-zero instructions
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support immediates in XVentanaCondOps
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add instruction fusion (for ventana-vt1)
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add basic support for the Ventana-VT1 core
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion
2022-11-18 20:23 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Replace zero_extendsidi2_shifted with generalized split
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: fold two bit tests with different polarity
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: recognize single bit test of sign-bit
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimise adding a (larger than simm12) constant to a register
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
2022-11-18 20:22 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero
2022-11-18 20:22 UTC
[gcc/vrull/heads/for-upstream] (38 commits) riscv: Add support for strlen inline expansion
2022-11-18 20:22 UTC
[gcc r13-4155] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs
2022-11-18 20:18 UTC
[gcc r13-4154] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori
2022-11-18 20:18 UTC
[gcc r13-4153] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w
2022-11-18 20:18 UTC
[gcc r13-4152] RISC-V: split to allow formation of sh[123]add before 32bit divw
2022-11-18 20:18 UTC
[gcc r13-4151] RISC-V: Optimize branches testing a bit-range or a shifted immediate
2022-11-18 20:18 UTC
[gcc r13-4150] RISC-V: allow bseti on SImode without sign-extension
2022-11-18 20:18 UTC
[gcc r13-4149] libcpp: Avoid remapping filenames within directives
2022-11-18 20:14 UTC
[gcc r13-4148] Manually add entries for r13-4128
2022-11-18 18:22 UTC
[gcc r13-4147] Fortran: reject NULL actual argument without explicit interface [PR107576]
2022-11-18 18:21 UTC
[gcc r12-8917] Daily bump
2022-11-18 18:13 UTC
[gcc r11-10382] Daily bump
2022-11-18 18:12 UTC
[gcc r10-11088] Daily bump
2022-11-18 18:10 UTC
[gcc r13-4146] Daily bump
2022-11-18 18:09 UTC
[gcc r13-4145] Add another commit to ignore
2022-11-18 18:06 UTC
[gcc r13-4144] Fix PR middle-end/107705: ICE after reclaration error
2022-11-18 17:03 UTC
[gcc r13-4143] Fix PRs 106764, 106765, and 107307, all ICE after invalid re-declaration
2022-11-18 17:03 UTC
[gcc(refs/vendors/ARM/heads/morello)] Handle MEM_REF[&<something>] in gimple
2022-11-18 16:11 UTC
[gcc r13-4142] Fix testcase for architectures that use .srodata
2022-11-18 15:48 UTC
[gcc r13-4141] aarch64: Fix LDAPURS assembly output
2022-11-18 14:57 UTC
[gcc/devel/modula-2] Revert sphinx and reintroduce texinfo make rules
2022-11-18 12:25 UTC
[gcc/devel/modula-2] Merge branch 'master' into devel/modula-2
2022-11-18 12:25 UTC
[gcc/devel/modula-2] (280 commits) Revert sphinx and reintroduce texinfo make rules
2022-11-18 12:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Add support for strlen inline expansion
2022-11-18 11:36 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Use by-pieces to do overlapping accesses in block_move_straight
2022-11-18 11:36 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Move riscv_block_move_loop to separate file
2022-11-18 11:36 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Enable overlap-by-pieces via tune param
2022-11-18 11:36 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity
2022-11-18 11:36 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use .p2align for code-alignment
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcvt: add if-conversion to conditional-zero instructions
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support immediates in XVentanaCondOps
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add instruction fusion (for ventana-vt1)
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add basic support for the Ventana-VT1 core
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs
2022-11-18 11:35 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Replace zero_extendsidi2_shifted with generalized split
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: fold two bit tests with different polarity
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: recognize single bit test of sign-bit
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimise adding a (larger than simm12) constant to a register
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimize branches testing a bit-range or a shifted immediate
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: allow bseti on SImode without sign-extension
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: split to allow formation of sh[123]add before 32bit divw
2022-11-18 11:34 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero
2022-11-18 11:34 UTC
[gcc/vrull/heads/for-upstream] (40 commits) riscv: Add support for strlen inline expansion
2022-11-18 11:33 UTC
[gcc r13-4140] testsuite: Verify that module-mapper is available
2022-11-18 10:31 UTC
[gcc/devel/omp/gcc-12] Merge branch 'releases/gcc-12' into devel/omp/gcc-12
2022-11-18 9:48 UTC
[gcc/devel/omp/gcc-12] gcn: Add __builtin_gcn_kernarg_ptr
2022-11-18 9:48 UTC
[gcc/devel/omp/gcc-12] (11 commits) Merge branch 'releases/gcc-12' into devel/omp/gcc-12
2022-11-18 9:48 UTC
[gcc r13-4139] aarch64: Fix up LDAPR codegen
2022-11-18 9:08 UTC
[gcc r13-4138] c++: Implement CWG2635 - Constrained structured bindings
2022-11-18 8:05 UTC
[gcc r13-4137] tree-optimization/107647 - avoid FMA from SLP with -ffp-contract=off
2022-11-18 7:37 UTC
[gcc r13-4136] LoongArch: Fix atomic_exchange expanding [PR107713]
2022-11-18 7:05 UTC
[gcc r10-11087] c++: constinit on pointer to function [PR104066]
2022-11-18 0:47 UTC
[gcc r11-10381] c++: constinit on pointer to function [PR104066]
2022-11-18 0:45 UTC
[gcc r12-8916] c++: constinit on pointer to function [PR104066]
2022-11-18 0:43 UTC
[gcc r13-4135] c++: constinit on pointer to function [PR104066]
2022-11-18 0:16 UTC
[gcc/devel/modula-2] Rebuilt libgm2 Makefile.in's
2022-11-17 22:36 UTC
[gcc/devel/modula-2] pge ebnf and def2doc.py first cut complete for Sphinx
2022-11-17 22:33 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 22:32 UTC
[gcc(refs/users/meissner/heads/dmf004)] Reset memcpy inline bytes parameter
2022-11-17 22:30 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Add support for strlen inline expansion
2022-11-17 22:27 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Use by-pieces to do overlapping accesses in block_move_straight
2022-11-17 22:27 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Move riscv_block_move_loop to separate file
2022-11-17 22:27 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: Enable overlap-by-pieces via tune param
2022-11-17 22:27 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use .p2align for code-alignment
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcvt: add if-conversion to conditional-zero instructions
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support immediates in XVentanaCondOps
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add instruction fusion (for ventana-vt1)
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Add basic support for the Ventana-VT1 core
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
2022-11-17 22:26 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use binvi to cover more immediates than with xori alone
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use bseti to cover more immediates than with ori alone
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Replace zero_extendsidi2_shifted with generalized split
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: fold two bit tests with different polarity
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] ifcombine: recognize single bit test of sign-bit
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimise adding a (larger than simm12) constant to a register
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: No extensions for SImode min/max against safe constant
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimize branches testing a bit-range or a shifted immediate
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: allow bseti on SImode without sign-extension
2022-11-17 22:25 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w
2022-11-17 22:24 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: split to allow formation of sh[123]add before 32bit divw
2022-11-17 22:24 UTC
[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero
2022-11-17 22:24 UTC
[gcc/vrull/heads/for-upstream] (101 commits) riscv: Add support for strlen inline expansion
2022-11-17 22:24 UTC
[gcc(refs/users/meissner/heads/dmf004)] Revert patch
2022-11-17 22:08 UTC
[gcc(refs/users/meissner/heads/dmf004)] Merge commit 'refs/users/meissner/heads/dmf004' of git+ssh://gcc.gnu.org/git/gcc into me/dmf004
2022-11-17 21:56 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:56 UTC
[gcc(refs/users/meissner/heads/dmf004)] Add suuport to use stxvl for variable sized memsets
2022-11-17 21:56 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Fix lxvl and stxvl wrong conditional branch
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Limit memcpy inline copy to do just 2 variable moves
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Add lxvprl and stxvprl support
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Tweak variable move support
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Don't do load/store vector with length if overlap
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Allow for inline code for memcpy to move more than 16 bytes
2022-11-17 21:55 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Add parameter for memcpy inline code moves
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Revert patch
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Add parameter for memcpy inline code moves
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Use lxvl and stxvl for small variable memcpy moves
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Revert patch
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner
2022-11-17 21:54 UTC
[gcc(refs/users/meissner/heads/dmf004)] Use lxvl and stxvl for small variable memcpy moves
2022-11-17 21:54 UTC
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