Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency

[Segher Boessenkool <segher@kernel.crashing.org>]

On Wed, Feb 16, 2022 at 11:41:37AM -0800, Reshabh K Sharma wrote:
> I wanted to add scheduling cost to rd and rs, I was suggested to use
> TARGET_SCHED_ADJUST_COST but there I need to check if the instruction is
> FLWR and as suggested I tried using get_attr_type. I realized that first I
> need to set the type then use get_attr_type. I also couldn't find any other
> place to set the attribute other than define_insn but this custom
> instruction was just going to be used in inline asm right now so there was
> no equivalent rtl from which I can lower into this but since I was not able
> to find any other way to set the attribute, I decided to add a pattern
> (hoping it to be unmatchable) where I could add the attribute, so inside
> riscv.md I added the define_insn for flwr and used set_attr but I'm not
> able to find any instruction in the TARGET_SCHED_ADJUST_COST for the
> specific type attr.
> 
> 1. Does inline asm compilation flow goes through the
> TARGET_SCHED_ADJUST_COST?
> 2. Is there a better way to do this? / Am I missing something?

GCC does not look at the assembler template to try to figure out what
instructions are in there.  This is by design.  So, the compiler can
never know much about how it will schedule on the real machine (it does
estimate (pessimistically) how big the resulting machine code will be,
so that any branches can reach their target).

Making a define_insn for your insn is exactly the right plan.  You do
not have too hope it does not accidentally match anything else: if you
make it an unspec, it can never match anything but itself (nothing with
a different "index" number).


Segher