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From: Reshabh K Sharma <reshabh@cs.washington.edu>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Jeff Law <jeffreyalaw@gmail.com>, gcc-help@gcc.gnu.org
Subject: Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency
Date: Wed, 16 Feb 2022 11:41:37 -0800	[thread overview]
Message-ID: <CAAhFPT2=c8M0VzmGmt+gQGLfp-+LiJpQPVzuXvq03aC7gSHENQ@mail.gmail.com> (raw)
In-Reply-To: <20220204013156.GD614@gate.crashing.org>

On Thu, Feb 3, 2022 at 5:33 PM Segher Boessenkool <
segher@kernel.crashing.org> wrote:

> Hi!
>
> On Thu, Feb 03, 2022 at 05:06:23PM -0800, Reshabh K Sharma wrote:
> > On Fri, Jan 28, 2022 at 10:23 AM Segher Boessenkool <
> > segher@kernel.crashing.org> wrote:
> > > You can use TARGET_SCHED_ADJUST_COST?
> >
> > Thank you so much! I think target_sched_adjust_cost will do.
> > Given two rtx_insn,
> > x = exp_load addr offset and
> > y = add addr z,
> > these two instructions are the input arguments to
> target_sched_adjust_cost,
> >
> > how do I check that given rtx_insn is exp_load? (how do we check if
> > rtx_insn is of type exp_load, add or any other target specific
> instruction?)
> > and how do I check if there is a read after read dependency for addr
> > operand and not the offset.
>
> "type" is just an insn attribute, so you would use
>   if (get_attr_type (insn) == TYPE_EXP_LOAD)
> or similar.
>

Thank you so much!

Initially I added an instruction in binutils inside opcode/riscv-opc.c as,
"{"flwr",      0, INSN_CLASS_I,   "D,s,t",  MATCH_FLWR, MASK_FLWR,
match_opcode, INSN_DREF|INSN_4_BYTE }," for a custom instruction, flwr rd,
rs1, rs2

I wanted to add scheduling cost to rd and rs, I was suggested to use
TARGET_SCHED_ADJUST_COST but there I need to check if the instruction is
FLWR and as suggested I tried using get_attr_type. I realized that first I
need to set the type then use get_attr_type. I also couldn't find any other
place to set the attribute other than define_insn but this custom
instruction was just going to be used in inline asm right now so there was
no equivalent rtl from which I can lower into this but since I was not able
to find any other way to set the attribute, I decided to add a pattern
(hoping it to be unmatchable) where I could add the attribute, so inside
riscv.md I added the define_insn for flwr and used set_attr but I'm not
able to find any instruction in the TARGET_SCHED_ADJUST_COST for the
specific type attr.

1. Does inline asm compilation flow goes through the
TARGET_SCHED_ADJUST_COST?
2. Is there a better way to do this? / Am I missing something?


> Segher
>

Many thanks,
Reshabh

  reply	other threads:[~2022-02-16 19:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-27  1:20 Reshabh K Sharma
2022-01-28 17:39 ` Jeff Law
2022-01-28 18:21   ` Segher Boessenkool
2022-02-04  1:06     ` Reshabh K Sharma
2022-02-04  1:31       ` Segher Boessenkool
2022-02-16 19:41         ` Reshabh K Sharma [this message]
2022-02-17 18:48           ` Segher Boessenkool

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