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* Complex half-word operations
@ 2011-10-18 16:31 Ayonam Ray
  2011-10-18 17:08 ` Ian Lance Taylor
  0 siblings, 1 reply; 7+ messages in thread
From: Ayonam Ray @ 2011-10-18 16:31 UTC (permalink / raw)
  To: gcc-help

I'm trying to define a complex half word operation (add:CHI) using the
following RTL:

(define_insn "addchi3"
  [(set (match_operand:CHI 0 "register_operand" "=r")
        (plus:CHI (match_operand:CHI 1 "register_operand" "r")
                  (match_operand:CHI 2 "register_operand" "r")))]
  ""
  "cmplxadd\t%1, %2, %0"
  [(set_attr "type" "complex")
   (set_attr "slot" "s1")
   (set_attr "predicable" "no")
   (set_attr "length" "4")])

This architecture can perform arithmetic operations on "complex short"
data by packing the real and imaginary parts into two half words of a
32-bit general register.

However, the instruction matcher doesn't seem to generate this RTL at
all.  It splits the operation into two half word additions.  I have
handled the CHImode in the macros HARD_REGNO_NREGS, and
HARD_REGNO_MODE_OK.  How do we tell GCC that the real and imaginary
parts are actually packed into a single register?  I tried defining
two RTLs to pack and unpack the two parts using the concat:CHI
operation.

Any help on this is much appreciated.
Thanks
Ayonam

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 16:31 Complex half-word operations Ayonam Ray
@ 2011-10-18 17:08 ` Ian Lance Taylor
  2011-10-18 17:20   ` Ayonam Ray
  0 siblings, 1 reply; 7+ messages in thread
From: Ian Lance Taylor @ 2011-10-18 17:08 UTC (permalink / raw)
  To: Ayonam Ray; +Cc: gcc-help

On Tue, Oct 18, 2011 at 9:30 AM, Ayonam Ray <ayonam@gmail.com> wrote:
> I'm trying to define a complex half word operation (add:CHI) using the
> following RTL:
>
> (define_insn "addchi3"
>   [(set (match_operand:CHI 0 "register_operand" "=r")
>         (plus:CHI (match_operand:CHI 1 "register_operand" "r")
>                   (match_operand:CHI 2 "register_operand" "r")))]
>   ""
>   "cmplxadd\t%1, %2, %0"
>   [(set_attr "type" "complex")
>    (set_attr "slot" "s1")
>    (set_attr "predicable" "no")
>    (set_attr "length" "4")])
>
> This architecture can perform arithmetic operations on "complex short"
> data by packing the real and imaginary parts into two half words of a
> 32-bit general register.
>
> However, the instruction matcher doesn't seem to generate this RTL at
> all.  It splits the operation into two half word additions.  I have
> handled the CHImode in the macros HARD_REGNO_NREGS, and
> HARD_REGNO_MODE_OK.  How do we tell GCC that the real and imaginary
> parts are actually packed into a single register?  I tried defining
> two RTLs to pack and unpack the two parts using the concat:CHI
> operation.

I don't think the gcc middle-end has any support for machines which provide
special handling for complex int.  I think the middle-end always breaks up
complex int operations into pairs of int operations.  So to make this work you
would probably have to add that support.

Ian

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 17:08 ` Ian Lance Taylor
@ 2011-10-18 17:20   ` Ayonam Ray
  2011-10-18 17:38     ` Ian Lance Taylor
  0 siblings, 1 reply; 7+ messages in thread
From: Ayonam Ray @ 2011-10-18 17:20 UTC (permalink / raw)
  To: Ian Lance Taylor; +Cc: gcc-help

On 18 October 2011 22:38, Ian Lance Taylor <iant@google.com> wrote:
> On Tue, Oct 18, 2011 at 9:30 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>> I'm trying to define a complex half word operation (add:CHI) using the
>> following RTL:
>>
>> (define_insn "addchi3"
>>   [(set (match_operand:CHI 0 "register_operand" "=r")
>>         (plus:CHI (match_operand:CHI 1 "register_operand" "r")
>>                   (match_operand:CHI 2 "register_operand" "r")))]
>>   ""
>>   "cmplxadd\t%1, %2, %0"
>>   [(set_attr "type" "complex")
>>    (set_attr "slot" "s1")
>>    (set_attr "predicable" "no")
>>    (set_attr "length" "4")])
>>
>> This architecture can perform arithmetic operations on "complex short"
>> data by packing the real and imaginary parts into two half words of a
>> 32-bit general register.
>>
>> However, the instruction matcher doesn't seem to generate this RTL at
>> all.  It splits the operation into two half word additions.  I have
>> handled the CHImode in the macros HARD_REGNO_NREGS, and
>> HARD_REGNO_MODE_OK.  How do we tell GCC that the real and imaginary
>> parts are actually packed into a single register?  I tried defining
>> two RTLs to pack and unpack the two parts using the concat:CHI
>> operation.
>
> I don't think the gcc middle-end has any support for machines which provide
> special handling for complex int.  I think the middle-end always breaks up
> complex int operations into pairs of int operations.  So to make this work you
> would probably have to add that support.
>
> Ian
>

Thanks Ian for the reply.  Can you please point me to the files in the
middle-end where I may find the relevant code?

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 17:20   ` Ayonam Ray
@ 2011-10-18 17:38     ` Ian Lance Taylor
  2011-10-18 17:46       ` Ayonam Ray
  0 siblings, 1 reply; 7+ messages in thread
From: Ian Lance Taylor @ 2011-10-18 17:38 UTC (permalink / raw)
  To: Ayonam Ray; +Cc: gcc-help

On Tue, Oct 18, 2011 at 10:20 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>> I don't think the gcc middle-end has any support for machines which provide
>> special handling for complex int.  I think the middle-end always breaks up
>> complex int operations into pairs of int operations.  So to make this work you
>> would probably have to add that support.
>>
>
> Thanks Ian for the reply.  Can you please point me to the files in the
> middle-end where I may find the relevant code?

There are probably multiple places to look.  I would start with genopinit.c
and expr.c.  Look for support for complex float and see how to add support
for complex int.  This won't be a simple task, and you'll need to have a
pretty clear understanding of how gcc works internally.

Ian

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 17:38     ` Ian Lance Taylor
@ 2011-10-18 17:46       ` Ayonam Ray
  2011-10-18 17:54         ` Ian Lance Taylor
  0 siblings, 1 reply; 7+ messages in thread
From: Ayonam Ray @ 2011-10-18 17:46 UTC (permalink / raw)
  To: Ian Lance Taylor; +Cc: gcc-help

On 18 October 2011 23:08, Ian Lance Taylor <iant@google.com> wrote:
> On Tue, Oct 18, 2011 at 10:20 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>>> I don't think the gcc middle-end has any support for machines which provide
>>> special handling for complex int.  I think the middle-end always breaks up
>>> complex int operations into pairs of int operations.  So to make this work you
>>> would probably have to add that support.
>>>
>>
>> Thanks Ian for the reply.  Can you please point me to the files in the
>> middle-end where I may find the relevant code?
>
> There are probably multiple places to look.  I would start with genopinit.c
> and expr.c.  Look for support for complex float and see how to add support
> for complex int.  This won't be a simple task, and you'll need to have a
> pretty clear understanding of how gcc works internally.
>
> Ian
>

Thanks again for the pointers.  Yes, I do appreciate that this won't
be a simple task.  I want to be able to scope the task for now.

Also, don't you think I need to add similar support to the other
passes down the line so that they understand the operation?  Any
pointers there?

Thanks much.
Ayonam

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 17:46       ` Ayonam Ray
@ 2011-10-18 17:54         ` Ian Lance Taylor
  2011-10-18 18:07           ` Ayonam Ray
  0 siblings, 1 reply; 7+ messages in thread
From: Ian Lance Taylor @ 2011-10-18 17:54 UTC (permalink / raw)
  To: Ayonam Ray; +Cc: gcc-help

On Tue, Oct 18, 2011 at 10:46 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>
> Also, don't you think I need to add similar support to the other
> passes down the line so that they understand the operation?  Any
> pointers there?

This is an RTL level thing.  The RTL level doesn't have any real understanding
of its operations anyhow.  The combine pass implements optimizations by simply
looking at patterns defined in the backend.  So while its possible that you will
need to add a few tweaks here and there, I would not expect that anything
major would be required once you're generating the right patterns.

Ian

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: Complex half-word operations
  2011-10-18 17:54         ` Ian Lance Taylor
@ 2011-10-18 18:07           ` Ayonam Ray
  0 siblings, 0 replies; 7+ messages in thread
From: Ayonam Ray @ 2011-10-18 18:07 UTC (permalink / raw)
  To: Ian Lance Taylor; +Cc: gcc-help

On 18 October 2011 23:23, Ian Lance Taylor <iant@google.com> wrote:
>
> This is an RTL level thing.  The RTL level doesn't have any real understanding
> of its operations anyhow.  The combine pass implements optimizations by simply
> looking at patterns defined in the backend.  So while its possible that you will
> need to add a few tweaks here and there, I would not expect that anything
> major would be required once you're generating the right patterns.
>
> Ian
>

Thanks Ian for the help.  Much appreciated.  This should get me going.

Regards
Ayonam

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2011-10-18 18:07 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-10-18 16:31 Complex half-word operations Ayonam Ray
2011-10-18 17:08 ` Ian Lance Taylor
2011-10-18 17:20   ` Ayonam Ray
2011-10-18 17:38     ` Ian Lance Taylor
2011-10-18 17:46       ` Ayonam Ray
2011-10-18 17:54         ` Ian Lance Taylor
2011-10-18 18:07           ` Ayonam Ray

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