Re: Re: [PATCH] RISC-V: Fine tune gather load RA constraint

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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Adding  earlyclobber is to make dest operand do not overlap with source operand.
For example:
for gather load, vluxei.v v8,(a5),v8 is illegal according to RVV ISA.
GCC is using same way as LLVM which is also adding earlyclobber for modeling disabling overlap between dest and source operand.



juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2023-04-22 04:36
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
 
 
On 3/13/23 02:28, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> For DEST EEW < SOURCE EEW, we can partial overlap register
> according to RVV ISA.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Fix RA constraint.
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/rvv/base/narrow_constraint-12.c: New test.
This is OK.
 
The one question I keep having when I read these patterns is why we have 
the earlyclobber.
 
Earlyclobber means that the output is potentially written before the 
inputs are consumed.   Typically for a single instruction pattern such 
constraints wouldn't make a lot of sense as *usually* the inputs are 
consumed before the output is written.
 
Just looking for a clarification as to why the earlyclobbers are needed 
at all, particularly for non-reduction patterns.
 
jeff