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From: Jeff Law <jeffreyalaw@gmail.com>
To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
Date: Fri, 21 Apr 2023 14:36:43 -0600	[thread overview]
Message-ID: <0c328c8e-21bc-5aee-af79-f53bd078c665@gmail.com> (raw)
In-Reply-To: <20230313082855.248118-1-juzhe.zhong@rivai.ai>



On 3/13/23 02:28, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> For DEST EEW < SOURCE EEW, we can partial overlap register
> according to RVV ISA.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Fix RA constraint.
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/rvv/base/narrow_constraint-12.c: New test.
This is OK.

The one question I keep having when I read these patterns is why we have 
the earlyclobber.

Earlyclobber means that the output is potentially written before the 
inputs are consumed.   Typically for a single instruction pattern such 
constraints wouldn't make a lot of sense as *usually* the inputs are 
consumed before the output is written.

Just looking for a clarification as to why the earlyclobbers are needed 
at all, particularly for non-reduction patterns.

jeff

  parent reply	other threads:[~2023-04-21 20:36 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-13  8:28 juzhe.zhong
2023-03-14 18:08 ` Jeff Law
2023-03-15  6:52   ` juzhe.zhong
2023-03-19 16:55     ` Jeff Law
2023-03-20  0:49       ` juzhe.zhong
2023-04-21 20:36 ` Jeff Law [this message]
2023-04-24  3:05   ` juzhe.zhong
2023-04-26  4:21     ` Kito Cheng

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