* [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
@ 2023-06-12 7:40 pan2.li
2023-06-12 7:42 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-06-12 7:40 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From
the user's perspective, it is reasonable to do some get/set operations
for the vfloat16*_t types when only ZVFHMIN is enabled.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat16m1_t): Add type to lmul1 ops.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Likewise.
---
.../riscv/riscv-vector-builtins-types.def | 3 ++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 15 +++++++--
.../riscv/rvv/base/zvfhmin-intrinsic.c | 32 ++++++++++++++-----
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index db8e61fea6a..4926bd8a2d2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -1091,6 +1091,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint16m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint32m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1102,6 +1103,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint16m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint32m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1113,6 +1115,7 @@ DEF_RVV_LMUL4_OPS (vuint8m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint16m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint32m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index c3ed4191a36..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -61,6 +61,14 @@ vfloat16m8_t test_vundefined_f16m8() {
return __riscv_vundefined_f16m8();
}
+vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
+ return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
+}
+
+vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
+ return __riscv_vget_v_f16m8_f16m4(src, 0);
+}
+
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
@@ -71,7 +79,10 @@ vfloat16m8_t test_vundefined_f16m8() {
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
-/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
-/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 8d39a2ed4c2..1026b3f82f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -165,6 +165,22 @@ vfloat16m8_t test_vundefined_f16m8() {
return __riscv_vundefined_f16m8();
}
+vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
+ return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
+}
+
+vfloat16m8_t test_vset_v_f16m4_f16m8(vfloat16m8_t dest, size_t index, vfloat16m4_t val) {
+ return __riscv_vset_v_f16m4_f16m8(dest, 0, val);
+}
+
+vfloat16m1_t test_vget_v_f16m2_f16m1(vfloat16m2_t src, size_t index) {
+ return __riscv_vget_v_f16m2_f16m1(src, 0);
+}
+
+vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
+ return __riscv_vget_v_f16m8_f16m4(src, 0);
+}
+
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
@@ -180,11 +196,11 @@ vfloat16m8_t test_vundefined_f16m8() {
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
-/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
+/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
2023-06-12 7:40 [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API pan2.li
@ 2023-06-12 7:42 ` juzhe.zhong
2023-06-12 12:48 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-06-12 7:42 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7653 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-06-12 15:40
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
From: Pan Li <pan2.li@intel.com>
This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From
the user's perspective, it is reasonable to do some get/set operations
for the vfloat16*_t types when only ZVFHMIN is enabled.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat16m1_t): Add type to lmul1 ops.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Likewise.
---
.../riscv/riscv-vector-builtins-types.def | 3 ++
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 15 +++++++--
.../riscv/rvv/base/zvfhmin-intrinsic.c | 32 ++++++++++++++-----
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index db8e61fea6a..4926bd8a2d2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -1091,6 +1091,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint16m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint32m1_t, 0)
DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1102,6 +1103,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint16m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint32m2_t, 0)
DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1113,6 +1115,7 @@ DEF_RVV_LMUL4_OPS (vuint8m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint16m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint32m4_t, 0)
DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index c3ed4191a36..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -61,6 +61,14 @@ vfloat16m8_t test_vundefined_f16m8() {
return __riscv_vundefined_f16m8();
}
+vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
+ return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
+}
+
+vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
+ return __riscv_vget_v_f16m8_f16m4(src, 0);
+}
+
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
@@ -71,7 +79,10 @@ vfloat16m8_t test_vundefined_f16m8() {
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
-/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
-/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 8d39a2ed4c2..1026b3f82f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -165,6 +165,22 @@ vfloat16m8_t test_vundefined_f16m8() {
return __riscv_vundefined_f16m8();
}
+vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
+ return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
+}
+
+vfloat16m8_t test_vset_v_f16m4_f16m8(vfloat16m8_t dest, size_t index, vfloat16m4_t val) {
+ return __riscv_vset_v_f16m4_f16m8(dest, 0, val);
+}
+
+vfloat16m1_t test_vget_v_f16m2_f16m1(vfloat16m2_t src, size_t index) {
+ return __riscv_vget_v_f16m2_f16m1(src, 0);
+}
+
+vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
+ return __riscv_vget_v_f16m8_f16m4(src, 0);
+}
+
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
@@ -180,11 +196,11 @@ vfloat16m8_t test_vundefined_f16m8() {
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
-/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
-/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
-/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
+/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
+/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
2023-06-12 7:42 ` juzhe.zhong
@ 2023-06-12 12:48 ` Kito Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Kito Cheng @ 2023-06-12 12:48 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
lgtm
On Mon, Jun 12, 2023 at 3:43 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-12 15:40
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From
> the user's perspective, it is reasonable to do some get/set operations
> for the vfloat16*_t types when only ZVFHMIN is enabled.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat16m1_t): Add type to lmul1 ops.
> (vfloat16m2_t): Likewise.
> (vfloat16m4_t): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Likewise.
> ---
> .../riscv/riscv-vector-builtins-types.def | 3 ++
> .../riscv/rvv/base/zvfh-over-zvfhmin.c | 15 +++++++--
> .../riscv/rvv/base/zvfhmin-intrinsic.c | 32 ++++++++++++++-----
> 3 files changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
> index db8e61fea6a..4926bd8a2d2 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -1091,6 +1091,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0)
> DEF_RVV_LMUL1_OPS (vuint16m1_t, 0)
> DEF_RVV_LMUL1_OPS (vuint32m1_t, 0)
> DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
> @@ -1102,6 +1103,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0)
> DEF_RVV_LMUL2_OPS (vuint16m2_t, 0)
> DEF_RVV_LMUL2_OPS (vuint32m2_t, 0)
> DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
> @@ -1113,6 +1115,7 @@ DEF_RVV_LMUL4_OPS (vuint8m4_t, 0)
> DEF_RVV_LMUL4_OPS (vuint16m4_t, 0)
> DEF_RVV_LMUL4_OPS (vuint32m4_t, 0)
> DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> index c3ed4191a36..1d82cc8de2d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> @@ -61,6 +61,14 @@ vfloat16m8_t test_vundefined_f16m8() {
> return __riscv_vundefined_f16m8();
> }
> +vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
> + return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
> +}
> +
> +vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
> + return __riscv_vget_v_f16m8_f16m4(src, 0);
> +}
> +
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> @@ -71,7 +79,10 @@ vfloat16m8_t test_vundefined_f16m8() {
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> /* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */
> /* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
> -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> /* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> /* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index 8d39a2ed4c2..1026b3f82f1 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -165,6 +165,22 @@ vfloat16m8_t test_vundefined_f16m8() {
> return __riscv_vundefined_f16m8();
> }
> +vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vfloat16m1_t val) {
> + return __riscv_vset_v_f16m1_f16m2(dest, 0, val);
> +}
> +
> +vfloat16m8_t test_vset_v_f16m4_f16m8(vfloat16m8_t dest, size_t index, vfloat16m4_t val) {
> + return __riscv_vset_v_f16m4_f16m8(dest, 0, val);
> +}
> +
> +vfloat16m1_t test_vget_v_f16m2_f16m1(vfloat16m2_t src, size_t index) {
> + return __riscv_vget_v_f16m2_f16m1(src, 0);
> +}
> +
> +vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {
> + return __riscv_vget_v_f16m8_f16m4(src, 0);
> +}
> +
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> @@ -180,11 +196,11 @@ vfloat16m8_t test_vundefined_f16m8() {
> /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
> /* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> -/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> -/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> +/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */
> +/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-06-12 12:48 UTC | newest]
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2023-06-12 7:40 [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API pan2.li
2023-06-12 7:42 ` juzhe.zhong
2023-06-12 12:48 ` Kito Cheng
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