* [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr
@ 2023-05-24 17:54 Roger Sayle
2023-05-25 16:58 ` Bernhard Reutner-Fischer
0 siblings, 1 reply; 5+ messages in thread
From: Roger Sayle @ 2023-05-24 17:54 UTC (permalink / raw)
To: gcc-patches; +Cc: 'Uros Bizjak'
[-- Attachment #1: Type: text/plain, Size: 975 bytes --]
My understanding is that GCC's preferred null value for rtx is NULL_RTX
(and for tree is NULL_TREE), and by being typed allows strict type checking,
and use with function polymorphism and template instantiation.
C++'s nullptr is preferred over NULL and 0 for pointer types that don't
have a defined null of the correct type.
This minor clean-up uses NULL_RTX consistently in i386-expand.cc.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures. Ok for mainline? Is my understanding correct?
2023-05-24 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386.cc (ix86_convert_wide_int_to_broadcast): Use
NULL_RTX instead of nullptr.
(ix86_convert_const_wide_int_to_broadcast): Likewise.
(ix86_broadcast_from_constant): Likewise.
(ix86_expand_vector_move): Likewise.
(ix86_extract_perm_from_pool_constant): Likewise.
Thanks,
Roger
--
[-- Attachment #2: patchnl.txt --]
[-- Type: text/plain, Size: 4953 bytes --]
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 634fe61..a867288 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -296,7 +296,7 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
/* Don't use integer vector broadcast if we can't move from GPR to SSE
register directly. */
if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
- return nullptr;
+ return NULL_RTX;
/* Convert CONST_WIDE_INT to a non-standard SSE constant integer
broadcast only if vector broadcast is available. */
@@ -305,7 +305,7 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
|| standard_sse_constant_p (op, mode)
|| (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT
!= GET_MODE_BITSIZE (mode)))
- return nullptr;
+ return NULL_RTX;
HOST_WIDE_INT val = CONST_WIDE_INT_ELT (op, 0);
HOST_WIDE_INT val_broadcast;
@@ -326,12 +326,12 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
val_broadcast))
broadcast_mode = DImode;
else
- return nullptr;
+ return NULL_RTX;
/* Check if OP can be broadcasted from VAL. */
for (int i = 1; i < CONST_WIDE_INT_NUNITS (op); i++)
if (val != CONST_WIDE_INT_ELT (op, i))
- return nullptr;
+ return NULL_RTX;
unsigned int nunits = (GET_MODE_SIZE (mode)
/ GET_MODE_SIZE (broadcast_mode));
@@ -525,7 +525,7 @@ ix86_expand_move (machine_mode mode, rtx operands[])
{
rtx tmp = ix86_convert_const_wide_int_to_broadcast
(GET_MODE (op0), op1);
- if (tmp != nullptr)
+ if (tmp != NULL_RTX)
op1 = tmp;
}
}
@@ -541,13 +541,13 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
{
int nunits = GET_MODE_NUNITS (mode);
if (nunits < 2)
- return nullptr;
+ return NULL_RTX;
/* Don't use integer vector broadcast if we can't move from GPR to SSE
register directly. */
if (!TARGET_INTER_UNIT_MOVES_TO_VEC
&& INTEGRAL_MODE_P (mode))
- return nullptr;
+ return NULL_RTX;
/* Convert CONST_VECTOR to a non-standard SSE constant integer
broadcast only if vector broadcast is available. */
@@ -557,7 +557,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
|| GET_MODE_INNER (mode) == DImode))
|| FLOAT_MODE_P (mode))
|| standard_sse_constant_p (op, mode))
- return nullptr;
+ return NULL_RTX;
/* Don't broadcast from a 64-bit integer constant in 32-bit mode.
We can still put 64-bit integer constant in memory when
@@ -565,14 +565,14 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
if (GET_MODE_INNER (mode) == DImode && !TARGET_64BIT
&& (!TARGET_AVX512F
|| (GET_MODE_SIZE (mode) < 64 && !TARGET_AVX512VL)))
- return nullptr;
+ return NULL_RTX;
if (GET_MODE_INNER (mode) == TImode)
- return nullptr;
+ return NULL_RTX;
rtx constant = get_pool_constant (XEXP (op, 0));
if (GET_CODE (constant) != CONST_VECTOR)
- return nullptr;
+ return NULL_RTX;
/* There could be some rtx like
(mem/u/c:V16QI (symbol_ref/u:DI ("*.LC1")))
@@ -581,8 +581,8 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
{
constant = simplify_subreg (mode, constant, GET_MODE (constant),
0);
- if (constant == nullptr || GET_CODE (constant) != CONST_VECTOR)
- return nullptr;
+ if (constant == NULL_RTX || GET_CODE (constant) != CONST_VECTOR)
+ return NULL_RTX;
}
rtx first = XVECEXP (constant, 0, 0);
@@ -592,7 +592,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
rtx tmp = XVECEXP (constant, 0, i);
/* Vector duplicate value. */
if (!rtx_equal_p (tmp, first))
- return nullptr;
+ return NULL_RTX;
}
return first;
@@ -641,7 +641,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
machine_mode mode = GET_MODE (op0);
rtx tmp = ix86_convert_const_wide_int_to_broadcast
(mode, op1);
- if (tmp == nullptr)
+ if (tmp == NULL_RTX)
op1 = validize_mem (force_const_mem (mode, op1));
else
op1 = tmp;
@@ -656,7 +656,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
&& CONSTANT_POOL_ADDRESS_P (XEXP (op1, 0))))
{
rtx first = ix86_broadcast_from_constant (mode, op1);
- if (first != nullptr)
+ if (first != NULL_RTX)
{
/* Broadcast to XMM/YMM/ZMM register from an integer
constant or scalar mem. */
@@ -5797,7 +5797,7 @@ ix86_extract_perm_from_pool_constant (int* perm, rtx mem)
{
constant = simplify_subreg (mode, constant, GET_MODE (constant), 0);
- if (constant == nullptr || GET_CODE (constant) != CONST_VECTOR)
+ if (constant == NULL_RTX || GET_CODE (constant) != CONST_VECTOR)
return false;
}
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr
2023-05-24 17:54 [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr Roger Sayle
@ 2023-05-25 16:58 ` Bernhard Reutner-Fischer
2023-05-26 8:31 ` Bernhard Reutner-Fischer
0 siblings, 1 reply; 5+ messages in thread
From: Bernhard Reutner-Fischer @ 2023-05-25 16:58 UTC (permalink / raw)
To: Roger Sayle; +Cc: rep.dot.nop, gcc-patches, 'Uros Bizjak', jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 1667 bytes --]
On Wed, 24 May 2023 18:54:06 +0100
"Roger Sayle" <roger@nextmovesoftware.com> wrote:
> My understanding is that GCC's preferred null value for rtx is NULL_RTX
> (and for tree is NULL_TREE), and by being typed allows strict type checking,
> and use with function polymorphism and template instantiation.
> C++'s nullptr is preferred over NULL and 0 for pointer types that don't
> have a defined null of the correct type.
>
> This minor clean-up uses NULL_RTX consistently in i386-expand.cc.
Oh. Well, i can't resist cleanups :)
Given
$ cat /tmp/inp0.c ; echo EOF
rtx myfunc (int i, int j)
{
rtx ret;
if (i)
return NULL;
if (j)
ret = NULL;
if (ret == NULL) {
ret = NULL_RTX;
}
if (!ret)
return (rtx)2;
return NULL_RTX;
}
EOF
$ spatch --c++=11 --smpl-spacing --in-place --sp-file ~/coccinelle/rtx-null.0.cocci /tmp/inp0.c
init_defs_builtins: /usr/bin/../lib/coccinelle/standard.h
--- /tmp/inp0.c
+++ /tmp/cocci-output-76891-58af4a-inp0.c
@@ -2,10 +2,10 @@ rtx myfunc (int i, int j)
{
rtx ret;
if (i)
- return NULL;
+ return NULL_RTX;
if (j)
- ret = NULL;
- if (ret == NULL) {
+ ret = NULL_RTX;
+ if (ret == NULL_RTX) {
ret = NULL_RTX;
}
if (!ret)
HANDLING: /tmp/inp0.c
diff =
So you if you would feel like, someone could
find ./ \( -name "testsuite" -o -name "contrib" -o -name "examples" -o -name ".git" -o -name "zlib" -o -name "intl" \) -prune -o \( -name "*.[chpx]*" -a -type f \) -exec spatch --c++=11 --smpl-spacing --in-place $opts --sp-file ~/coccinelle/rtx-null.0.cocci {} \;
with the attached rtx-null coccinelle script.
(and handle nullptr too, and the same game for tree)
Just a thought..
[-- Attachment #2: rtx-null.0.cocci --]
[-- Type: application/octet-stream, Size: 601 bytes --]
// use NULL_RTX for rtx
// Idea stolen from Roger
@ assignment @
typedef rtx;
local idexpression rtx rr;
@@
-rr = NULL;
+rr = NULL_RTX;
@ ne @
typedef rtx;
local idexpression rtx rr;
@@
-rr != NULL;
+rr != NULL_RTX;
@ eq @
typedef rtx;
local idexpression rtx rr;
// override the metavariable NULL
// We want to retain the negation in if (!the_rtx) and not the_rtx == NULL_RTX
identifier NULL =~ "NULL";
@@
-rr == NULL
+rr == NULL_RTX
@ ret_null @
typedef rtx;
identifier fn;
// override the metavariable NULL
identifier NULL =~ "NULL";
@@
rtx fn (...)
{
...
-return NULL;
+return NULL_RTX;
...
}
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr
2023-05-25 16:58 ` Bernhard Reutner-Fischer
@ 2023-05-26 8:31 ` Bernhard Reutner-Fischer
2023-06-14 19:14 ` Bernhard Reutner-Fischer
0 siblings, 1 reply; 5+ messages in thread
From: Bernhard Reutner-Fischer @ 2023-05-26 8:31 UTC (permalink / raw)
To: Roger Sayle; +Cc: rep.dot.nop, gcc-patches, 'Uros Bizjak', jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 1242 bytes --]
On Thu, 25 May 2023 18:58:04 +0200
Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
> On Wed, 24 May 2023 18:54:06 +0100
> "Roger Sayle" <roger@nextmovesoftware.com> wrote:
>
> > My understanding is that GCC's preferred null value for rtx is NULL_RTX
> > (and for tree is NULL_TREE), and by being typed allows strict type checking,
> > and use with function polymorphism and template instantiation.
> > C++'s nullptr is preferred over NULL and 0 for pointer types that don't
> > have a defined null of the correct type.
> >
> > This minor clean-up uses NULL_RTX consistently in i386-expand.cc.
>
> Oh. Well, i can't resist cleanups :)
> (and handle nullptr too, and the same game for tree)
so like the attached. And
sed -e 's/RTX/TREE/g' -e 's/rtx/tree/g' \
< ~/coccinelle/gcc-rtx-null.0.cocci \
> ~/coccinelle/gcc-tree-null.0.cocci
I do not know if we want to shorten explicit NULL comparisons.
foo == NULL => !foo and foo != NULL => foo
Left them alone in the form they were written.
See the attached result of the rtx hunks, someone would have to build
it and hack git-commit-mklog.py --changelog 'Use NULL_RTX.'
to print("{}.".format(random.choice(['Ditto', 'Same', 'Likewise']))) ;)
>
> Just a thought..
cheers,
[-- Attachment #2: gcc-rtx-null.0.cocci --]
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// use NULL_RTX for rtx
// Idea stolen from Roger
@ assignment @
typedef rtx;
local idexpression rtx rr;
identifier NULL =~ "NULL|nullptr";
@@
-rr = NULL
+rr = NULL_RTX
@ ne @
typedef rtx;
local idexpression rtx rr;
identifier NULL =~ "NULL|nullptr";
@@
-rr != NULL
+rr != NULL_RTX
@ eq @
typedef rtx;
local idexpression rtx rr;
// override the metavariable NULL
// We want to retain the negation in if (!the_rtx) and not the_rtx == NULL_RTX
identifier NULL =~ "NULL|nullptr";
@@
-rr == NULL
+rr == NULL_RTX
@ ret_null @
typedef rtx;
identifier fn;
identifier NULL =~ "NULL";
symbol nullptr;
@@
rtx fn (...)
{
<...
-return \( NULL \| nullptr \);
+return NULL_RTX;
...>
}
// EOF
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diff --git a/gcc/alias.cc b/gcc/alias.cc
index 7dc7e06de07..f1925ab3de2 100644
--- a/gcc/alias.cc
+++ b/gcc/alias.cc
@@ -1725,7 +1725,7 @@ get_reg_known_value (unsigned int regno)
if (regno < vec_safe_length (reg_known_value))
return (*reg_known_value)[regno];
}
- return NULL;
+ return NULL_RTX;
}
/* Set it. */
diff --git a/gcc/auto-inc-dec.cc b/gcc/auto-inc-dec.cc
index 1486e8c679a..568fae7b906 100644
--- a/gcc/auto-inc-dec.cc
+++ b/gcc/auto-inc-dec.cc
@@ -428,7 +428,7 @@ move_dead_notes (rtx_insn *to_insn, rtx_insn *from_insn, rtx pattern)
{
rtx note;
rtx next_note;
- rtx prev_note = NULL;
+ rtx prev_note = NULL_RTX;
for (note = REG_NOTES (from_insn); note; note = next_note)
{
diff --git a/gcc/bb-reorder.cc b/gcc/bb-reorder.cc
index 615d5426a34..e42e4593a6a 100644
--- a/gcc/bb-reorder.cc
+++ b/gcc/bb-reorder.cc
@@ -1477,7 +1477,7 @@ sjlj_fix_up_crossing_landing_pad (basic_block old_bb)
rtx_insn *insn = BB_END (e->src);
rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
- gcc_assert (note != NULL);
+ gcc_assert (note != NULL_RTX);
const unsigned old_index = INTVAL (XEXP (note, 0));
/* Generate the new landing-pad structure. */
@@ -1525,7 +1525,7 @@ dw2_fix_up_crossing_landing_pad (eh_landing_pad old_lp, basic_block old_bb)
rtx_insn *insn = BB_END (e->src);
rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
- gcc_assert (note != NULL);
+ gcc_assert (note != NULL_RTX);
gcc_checking_assert (INTVAL (XEXP (note, 0)) == old_lp->index);
XEXP (note, 0) = GEN_INT (new_lp->index);
diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index 8400adaf5b4..48df3d4d193 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -985,7 +985,7 @@ expand_builtin_setjmp_receiver (rtx receiver_label)
}
}
- if (receiver_label != NULL && targetm.have_builtin_setjmp_receiver ())
+ if (receiver_label != NULL_RTX && targetm.have_builtin_setjmp_receiver ())
emit_insn (targetm.gen_builtin_setjmp_receiver (receiver_label));
else if (targetm.have_nonlocal_goto_receiver ())
emit_insn (targetm.gen_nonlocal_goto_receiver ());
@@ -4118,7 +4118,7 @@ expand_builtin_strncpy (tree exp, rtx target)
static rtx
gen_memset_value_from_prev (by_pieces_prev *prev, fixed_size_mode mode)
{
- rtx target = nullptr;
+ rtx target = NULL_RTX;
if (prev != nullptr && prev->data != nullptr)
{
/* Use the previous data in the same mode. */
@@ -4179,7 +4179,7 @@ gen_memset_value_from_prev (by_pieces_prev *prev, fixed_size_mode mode)
break;
}
}
- if (target == nullptr)
+ if (target == NULL_RTX)
prev_rtx = copy_to_reg (prev_rtx);
}
@@ -4203,7 +4203,7 @@ builtin_memset_read_str (void *data, void *prev,
rtx target = gen_memset_value_from_prev ((by_pieces_prev *) prev,
mode);
- if (target != nullptr)
+ if (target != NULL_RTX)
return target;
rtx src = gen_int_mode (*c, QImode);
@@ -4250,7 +4250,7 @@ builtin_memset_gen_str (void *data, void *prev,
return (rtx) data;
target = gen_memset_value_from_prev ((by_pieces_prev *) prev, mode);
- if (target != nullptr)
+ if (target != NULL_RTX)
return target;
if (VECTOR_MODE_P (mode))
@@ -6278,11 +6278,11 @@ expand_builtin_atomic_compare_exchange (machine_mode mode, tree exp,
is_weak = true;
if (target == const0_rtx)
- target = NULL;
+ target = NULL_RTX;
/* Lest the rtl backend create a race condition with an imporoper store
to memory, always create a new pseudo for OLDVAL. */
- oldval = NULL;
+ oldval = NULL_RTX;
if (!expand_atomic_compare_and_swap (&target, &oldval, mem, expect, desired,
is_weak, success, failure))
@@ -6387,8 +6387,8 @@ expand_ifn_atomic_compare_exchange (gcall *call)
bool is_weak = (tree_to_shwi (gimple_call_arg (call, 3)) & 256) != 0;
- rtx boolret = NULL;
- rtx oldval = NULL;
+ rtx boolret = NULL_RTX;
+ rtx oldval = NULL_RTX;
if (!expand_atomic_compare_and_swap (&boolret, &oldval, mem, expect, desired,
is_weak, success, failure))
@@ -7315,7 +7315,7 @@ expand_speculation_safe_value (machine_mode mode, tree exp, rtx target,
return const0_rtx;
/* If we don't have a suitable target, create one to hold the result. */
- if (target == NULL || GET_MODE (target) != mode)
+ if (target == NULL_RTX || GET_MODE (target) != mode)
target = gen_reg_rtx (mode);
if (GET_MODE (val) != mode && GET_MODE (val) != VOIDmode)
diff --git a/gcc/calls.cc b/gcc/calls.cc
index 1c9abccef68..2fa52d175d5 100644
--- a/gcc/calls.cc
+++ b/gcc/calls.cc
@@ -1907,7 +1907,7 @@ rtx
rtx_for_static_chain (const_tree fndecl_or_type, bool incoming_p)
{
if (DECL_P (fndecl_or_type) && !DECL_STATIC_CHAIN (fndecl_or_type))
- return NULL;
+ return NULL_RTX;
return targetm.calls.static_chain (fndecl_or_type, incoming_p);
}
diff --git a/gcc/ccmp.cc b/gcc/ccmp.cc
index 1bd6fadea35..d7ea6bff7c9 100644
--- a/gcc/ccmp.cc
+++ b/gcc/ccmp.cc
@@ -221,7 +221,7 @@ expand_ccmp_expr_1 (gimple *g, rtx_insn **prep_seq, rtx_insn **gen_seq)
rtx_insn *prep_seq_1, *gen_seq_1;
tmp = targetm.gen_ccmp_first (&prep_seq_1, &gen_seq_1, rcode0,
logical_op0_rhs1, logical_op0_rhs2);
- if (tmp != NULL)
+ if (tmp != NULL_RTX)
{
ret = expand_ccmp_next (op1, code, tmp, &prep_seq_1, &gen_seq_1);
cost1 = seq_cost (prep_seq_1, speed_p);
@@ -233,12 +233,12 @@ expand_ccmp_expr_1 (gimple *g, rtx_insn **prep_seq, rtx_insn **gen_seq)
If gs0 and gs1 are complex, the cost will be high, so avoid
reevaluation if above an arbitrary threshold. */
rtx_insn *prep_seq_2, *gen_seq_2;
- if (tmp == NULL || cost1 < COSTS_N_INSNS (25))
+ if (tmp == NULL_RTX || cost1 < COSTS_N_INSNS (25))
tmp2 = targetm.gen_ccmp_first (&prep_seq_2, &gen_seq_2, rcode1,
logical_op1_rhs1, logical_op1_rhs2);
if (!tmp && !tmp2)
return NULL_RTX;
- if (tmp2 != NULL)
+ if (tmp2 != NULL_RTX)
{
ret2 = expand_ccmp_next (op0, code, tmp2, &prep_seq_2,
&gen_seq_2);
diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc
index 85a93a547c0..f687bc86ca1 100644
--- a/gcc/cfgexpand.cc
+++ b/gcc/cfgexpand.cc
@@ -6496,10 +6496,10 @@ expand_stack_alignment (void)
drap_rtx = targetm.calls.get_drap_rtx ();
/* stack_realign_drap and drap_rtx must match. */
- gcc_assert ((stack_realign_drap != 0) == (drap_rtx != NULL));
+ gcc_assert ((stack_realign_drap != 0) == (drap_rtx != NULL_RTX));
/* Do nothing if NULL is returned, which means DRAP is not needed. */
- if (drap_rtx != NULL)
+ if (drap_rtx != NULL_RTX)
{
crtl->args.internal_arg_pointer = drap_rtx;
diff --git a/gcc/combine-stack-adj.cc b/gcc/combine-stack-adj.cc
index e479aea71a1..dfc8a57a06c 100644
--- a/gcc/combine-stack-adj.cc
+++ b/gcc/combine-stack-adj.cc
@@ -378,7 +378,7 @@ maybe_move_args_size_note (rtx_insn *last, rtx_insn *insn, bool after)
rtx note, last_note;
note = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
- if (note == NULL)
+ if (note == NULL_RTX)
return;
last_note = find_reg_note (last, REG_ARGS_SIZE, NULL_RTX);
@@ -399,19 +399,19 @@ maybe_move_args_size_note (rtx_insn *last, rtx_insn *insn, bool after)
static void
maybe_merge_cfa_adjust (rtx_insn *dst, rtx_insn *src, bool after)
{
- rtx snote = NULL, dnote = NULL;
+ rtx snote = NULL_RTX, dnote = NULL_RTX;
rtx sexp, dexp;
rtx exp1, exp2;
if (RTX_FRAME_RELATED_P (src))
snote = find_reg_note (src, REG_CFA_ADJUST_CFA, NULL_RTX);
- if (snote == NULL)
+ if (snote == NULL_RTX)
return;
sexp = XEXP (snote, 0);
if (RTX_FRAME_RELATED_P (dst))
dnote = find_reg_note (dst, REG_CFA_ADJUST_CFA, NULL_RTX);
- if (dnote == NULL)
+ if (dnote == NULL_RTX)
{
add_reg_note (dst, REG_CFA_ADJUST_CFA, sexp);
return;
@@ -473,7 +473,7 @@ force_move_args_size_note (basic_block bb, rtx_insn *prev, rtx_insn *insn)
/* First, make sure there's anything that needs doing. */
note = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
- if (note == NULL)
+ if (note == NULL_RTX)
return;
/* We need to find a spot between the previous and next exception points
diff --git a/gcc/combine.cc b/gcc/combine.cc
index a23caeed96f..717b1e142b5 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -10276,7 +10276,7 @@ reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
REGNO (x)))))
{
*result = rsp->last_set_sign_bit_copies;
- return NULL;
+ return NULL_RTX;
}
tem = get_last_value (x);
@@ -10287,7 +10287,7 @@ reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
&& GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
*result = rsp->sign_bit_copies;
- return NULL;
+ return NULL_RTX;
}
\f
/* Return the number of "extended" bits there are in X, when interpreted
@@ -11779,7 +11779,7 @@ gen_lowpart_for_combine (machine_mode omode, rtx x)
{
imode = int_mode_for_mode (omode).require ();
x = gen_lowpart_common (imode, x);
- if (x == NULL)
+ if (x == NULL_RTX)
goto fail;
}
res = lowpart_subreg (omode, x, imode);
diff --git a/gcc/compare-elim.cc b/gcc/compare-elim.cc
index c59dc0cf5a5..ef5b96ccc67 100644
--- a/gcc/compare-elim.cc
+++ b/gcc/compare-elim.cc
@@ -156,19 +156,19 @@ conforming_compare (rtx_insn *insn)
rtx set, src, dest;
set = single_set (insn);
- if (set == NULL)
- return NULL;
+ if (set == NULL_RTX)
+ return NULL_RTX;
src = SET_SRC (set);
if (GET_CODE (src) != COMPARE)
- return NULL;
+ return NULL_RTX;
dest = SET_DEST (set);
if (!REG_P (dest) || REGNO (dest) != targetm.flags_regnum)
- return NULL;
+ return NULL_RTX;
if (!REG_P (strip_not (XEXP (src, 0))))
- return NULL;
+ return NULL_RTX;
if (CONSTANT_P (XEXP (src, 1)) || REG_P (XEXP (src, 1)))
return src;
@@ -177,11 +177,11 @@ conforming_compare (rtx_insn *insn)
{
for (int i = 0; i < XVECLEN (XEXP (src, 1), 0); i++)
if (!REG_P (XVECEXP (XEXP (src, 1), 0, i)))
- return NULL;
+ return NULL_RTX;
return src;
}
- return NULL;
+ return NULL_RTX;
}
/* Look for a pattern of the "correct" form for an insn with a flags clobber
@@ -373,7 +373,7 @@ find_comparison_dom_walker::before_dom_children (basic_block bb)
src = conforming_compare (insn);
if (src)
{
- rtx eh_note = NULL;
+ rtx eh_note = NULL_RTX;
if (cfun->can_throw_non_call_exceptions)
eh_note = find_reg_note (insn, REG_EH_REGION, NULL);
@@ -507,17 +507,17 @@ maybe_select_cc_mode (struct comparison *cmp, rtx a ATTRIBUTE_UNUSED,
{
machine_mode sel_mode;
const int n = cmp->n_uses;
- rtx flags = NULL;
+ rtx flags = NULL_RTX;
#ifndef SELECT_CC_MODE
/* Minimize code differences when this target macro is undefined. */
- return NULL;
+ return NULL_RTX;
#define SELECT_CC_MODE(A,B,C) (gcc_unreachable (), VOIDmode)
#endif
/* If we don't have access to all of the uses, we can't validate. */
if (cmp->missing_uses || n == 0)
- return NULL;
+ return NULL_RTX;
/* Find a new mode that works for all of the uses. Special case the
common case of exactly one use. */
@@ -542,7 +542,7 @@ maybe_select_cc_mode (struct comparison *cmp, rtx a ATTRIBUTE_UNUSED,
{
sel_mode = targetm.cc_modes_compatible (sel_mode, new_mode);
if (sel_mode == VOIDmode)
- return NULL;
+ return NULL_RTX;
}
}
@@ -858,7 +858,7 @@ try_eliminate_compare (struct comparison *cmp)
/* Determine if we ought to use a different CC_MODE here. */
flags = maybe_select_cc_mode (cmp, cmp_a, cmp_b);
- if (flags == NULL)
+ if (flags == NULL_RTX)
flags = gen_rtx_REG (cmp->orig_mode, targetm.flags_regnum);
/* Generate a new comparison for installation in the setter. */
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index cb6aae3f1fa..cb83f44fbf1 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2573,7 +2573,7 @@ aarch64_expand_builtin_memtag (int fcode, tree exp, rtx target)
return const0_rtx;
}
- rtx pat = NULL;
+ rtx pat = NULL_RTX;
enum insn_code icode = aarch64_memtag_builtin_data[fcode -
AARCH64_MEMTAG_BUILTIN_START - 1].icode;
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index d6fc94015fa..fc01e1a6b50 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -4515,7 +4515,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
initialized. For that case no need to generate the first adrp
instruction as the final cost for global variable access is
one instruction. */
- if (gp_rtx != NULL)
+ if (gp_rtx != NULL_RTX)
{
/* -fpic for -mcmodel=small allow 32K GOT table size (but we are
using the page base as GOT base, the first page may be wasted,
@@ -4888,7 +4888,7 @@ aarch64_zero_extend_const_eq (machine_mode xmode, rtx x,
machine_mode ymode, rtx y)
{
rtx r = simplify_const_unary_operation (ZERO_EXTEND, xmode, y, ymode);
- gcc_assert (r != NULL);
+ gcc_assert (r != NULL_RTX);
return rtx_equal_p (x, r);
}
@@ -10205,7 +10205,7 @@ aarch64_expand_epilogue (bool for_sibcall)
unsigned reg2 = cfun->machine->frame.wb_pop_candidate2;
unsigned int last_gpr = (cfun->machine->frame.is_scs_enabled
? R29_REGNUM : R30_REGNUM);
- rtx cfi_ops = NULL;
+ rtx cfi_ops = NULL_RTX;
rtx_insn *insn;
/* A stack clash protection prologue may not have left EP0_REGNUM or
EP1_REGNUM in a usable state. The same is true for allocations
@@ -10299,7 +10299,7 @@ aarch64_expand_epilogue (bool for_sibcall)
rtx new_cfa = plus_constant (Pmode, stack_pointer_rtx, initial_adjust);
REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
RTX_FRAME_RELATED_P (insn) = 1;
- cfi_ops = NULL;
+ cfi_ops = NULL_RTX;
}
/* Liveness of EP0_REGNUM can not be trusted across function calls either, so
@@ -12147,7 +12147,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
/* Fall through */
case 0:
- if (x == NULL)
+ if (x == NULL_RTX)
{
output_operand_lossage ("missing operand");
return;
@@ -27472,7 +27472,7 @@ aarch64_sls_emit_blr_function_thunks (FILE *out_file)
for (int regnum = 0; regnum < 30; ++regnum)
{
rtx specu_label = cfun->machine->call_via[regnum];
- if (specu_label == NULL)
+ if (specu_label == NULL_RTX)
continue;
targetm.asm_out.print_operand (out_file, specu_label, 0);
diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc
index 360b50e20d4..4afa5132a27 100644
--- a/gcc/config/alpha/alpha.cc
+++ b/gcc/config/alpha/alpha.cc
@@ -1129,7 +1129,7 @@ alpha_legitimize_address_1 (rtx x, rtx scratch, machine_mode mode)
}
}
- return NULL;
+ return NULL_RTX;
split_addend:
{
@@ -4410,7 +4410,7 @@ alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val, rtx before,
emit_label (label);
label = gen_rtx_LABEL_REF (DImode, label);
- if (before == NULL)
+ if (before == NULL_RTX)
before = scratch;
emit_insn (gen_load_locked (mode, before, mem));
@@ -4884,7 +4884,7 @@ alpha_gp_save_rtx (void)
rtx_insn *seq;
rtx m = cfun->machine->gp_save_rtx;
- if (m == NULL)
+ if (m == NULL_RTX)
{
start_sequence ();
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index dd012ffa975..3604a1fc188 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -6481,7 +6481,7 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code)
case UNSPEC:
const char *suffix;
bool pcrel; pcrel = false;
- rtx base; base = NULL;
+ rtx base; base = NULL_RTX;
gcc_assert (XVECLEN (x, 0) >= 1);
switch (XINT (x, 1))
{
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index c3e731b8982..10d53c8a623 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -6777,7 +6777,7 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
const_tree type ATTRIBUTE_UNUSED)
{
if (!use_vfp_abi (pcs_variant, false))
- return NULL;
+ return NULL_RTX;
if (mode == BLKmode
|| (GET_MODE_CLASS (mode) == MODE_INT
@@ -9459,7 +9459,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
{
if (arm_tls_referenced_p (x))
{
- rtx addend = NULL;
+ rtx addend = NULL_RTX;
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
{
@@ -10106,7 +10106,7 @@ shifter_op_p (rtx op, rtx *shift_reg)
return XEXP (op, 0);
}
- return NULL;
+ return NULL_RTX;
}
static bool
@@ -10667,7 +10667,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (mode == SImode)
{
- rtx shift_by_reg = NULL;
+ rtx shift_by_reg = NULL_RTX;
rtx shift_op;
rtx non_shift_op;
rtx op0 = XEXP (x, 0);
@@ -10710,7 +10710,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
}
shift_op = shifter_op_p (op0, &shift_by_reg);
- if (shift_op == NULL)
+ if (shift_op == NULL_RTX)
{
shift_op = shifter_op_p (op1, &shift_by_reg);
non_shift_op = op0;
@@ -10718,9 +10718,9 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
else
non_shift_op = op1;
- if (shift_op != NULL)
+ if (shift_op != NULL_RTX)
{
- if (shift_by_reg != NULL)
+ if (shift_by_reg != NULL_RTX)
{
if (speed_p)
*cost += extra_cost->alu.arith_shift_reg;
@@ -10771,7 +10771,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
&& GET_MODE_SIZE (mode) < 4)
{
rtx shift_op, shift_reg;
- shift_reg = NULL;
+ shift_reg = NULL_RTX;
/* We check both sides of the MINUS for shifter operands since,
unlike PLUS, it's not commutative. */
@@ -10886,7 +10886,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
&& GET_MODE_SIZE (mode) < 4)
{
rtx shift_op, shift_reg;
- shift_reg = NULL;
+ shift_reg = NULL_RTX;
HANDLE_NARROW_SHIFT_ARITH (PLUS, 0);
@@ -10963,9 +10963,9 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
return true;
}
- shift_reg = NULL;
+ shift_reg = NULL_RTX;
shift_op = shifter_op_p (op0, &shift_reg);
- if (shift_op != NULL)
+ if (shift_op != NULL_RTX)
{
if (shift_reg)
{
@@ -11119,9 +11119,9 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
|| (code == IOR && TARGET_THUMB2)))
op0 = XEXP (op0, 0);
- shift_reg = NULL;
+ shift_reg = NULL_RTX;
shift_op = shifter_op_p (op0, &shift_reg);
- if (shift_op != NULL)
+ if (shift_op != NULL_RTX)
{
if (shift_reg)
{
@@ -11366,13 +11366,13 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (mode == SImode)
{
rtx shift_op;
- rtx shift_reg = NULL;
+ rtx shift_reg = NULL_RTX;
shift_op = shifter_op_p (XEXP (x, 0), &shift_reg);
if (shift_op)
{
- if (shift_reg != NULL)
+ if (shift_reg != NULL_RTX)
{
if (speed_p)
*cost += extra_cost->alu.log_shift_reg;
@@ -11500,11 +11500,11 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
return true;
}
- shift_reg = NULL;
+ shift_reg = NULL_RTX;
shift_op = shifter_op_p (XEXP (x, 0), &shift_reg);
- if (shift_op != NULL)
+ if (shift_op != NULL_RTX)
{
- if (shift_reg != NULL)
+ if (shift_reg != NULL_RTX)
{
*cost += rtx_cost (shift_reg, op0mode, ASHIFT,
1, speed_p);
@@ -13423,7 +13423,7 @@ neon_make_constant (rtx vals, bool generate)
else
gcc_unreachable ();
- if (const_vec != NULL
+ if (const_vec != NULL_RTX
&& simd_immediate_valid_for_move (const_vec, mode, NULL, NULL))
/* Load using VMOV. On Cortex-A8 this takes one cycle. */
return const_vec;
@@ -14772,7 +14772,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS];
int order[MAX_LDM_STM_OPS];
int base_reg = -1;
- rtx base_reg_rtx = NULL;
+ rtx base_reg_rtx = NULL_RTX;
int i, stm_case;
/* Write back of base register is currently only supported for Thumb 1. */
@@ -15317,7 +15317,7 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
HOST_WIDE_INT i, j;
HOST_WIDE_INT remaining = length, words;
- rtx halfword_tmp = NULL, byte_tmp = NULL;
+ rtx halfword_tmp = NULL_RTX, byte_tmp = NULL_RTX;
rtx dst, src;
bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
@@ -15468,7 +15468,7 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
emit_insn (gen_unaligned_storehi (mem,
gen_lowpart (HImode, halfword_tmp)));
- halfword_tmp = NULL;
+ halfword_tmp = NULL_RTX;
dstoffset += 2;
}
@@ -15493,7 +15493,7 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc);
mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
- byte_tmp = NULL;
+ byte_tmp = NULL_RTX;
dstoffset++;
}
@@ -15641,7 +15641,7 @@ arm_gen_cpymemqi (rtx *operands)
HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
HOST_WIDE_INT srcoffset, dstoffset;
rtx src, dst, srcbase, dstbase;
- rtx part_bytes_reg = NULL;
+ rtx part_bytes_reg = NULL_RTX;
rtx mem;
if (!CONST_INT_P (operands[2])
@@ -16596,7 +16596,7 @@ arm_reload_in_hi (rtx *operands)
/* PR 62554: If there is no equivalent memory location then just move
the value as an SImode register move. This happens when the target
architecture variant does not have an HImode register move. */
- if (base == NULL)
+ if (base == NULL_RTX)
{
gcc_assert (REG_P (operands[0]));
emit_insn (gen_movsi (gen_rtx_SUBREG (SImode, operands[0], 0),
@@ -16724,7 +16724,7 @@ arm_reload_out_hi (rtx *operands)
/* PR 62254: If there is no equivalent memory location then just move
the value as an SImode register move. This happens when the target
architecture variant does not have an HImode register move. */
- if (base == NULL)
+ if (base == NULL_RTX)
{
gcc_assert (REG_P (outval) || SUBREG_P (outval));
@@ -19231,7 +19231,7 @@ thumb1_reorg (void)
FOR_EACH_BB_FN (bb, cfun)
{
rtx dest, src;
- rtx cmp, op0, op1, set = NULL;
+ rtx cmp, op0, op1, set = NULL_RTX;
rtx_insn *prev, *insn = BB_END (bb);
bool insn_clobbered = false;
@@ -21915,7 +21915,7 @@ arm_output_function_epilogue (FILE *)
{
rtx label = cfun->machine->call_via[regno];
- if (label != NULL)
+ if (label != NULL_RTX)
{
switch_to_section (function_section (current_function_decl));
targetm.asm_out.internal_label (asm_out_file, "L",
@@ -30091,7 +30091,7 @@ arm_unwind_emit (FILE * out_file, rtx_insn *insn)
case REG_CFA_REGISTER:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
{
pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL)
@@ -32304,11 +32304,11 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
&& (((REG_P (amount) || SUBREG_P (amount))
&& GET_MODE (amount) == SImode)
|| CONST_INT_P (amount)));
- gcc_assert (scratch1 == NULL
+ gcc_assert (scratch1 == NULL_RTX
|| (GET_CODE (scratch1) == SCRATCH)
|| (GET_MODE (scratch1) == SImode
&& REG_P (scratch1)));
- gcc_assert (scratch2 == NULL
+ gcc_assert (scratch2 == NULL_RTX
|| (GET_CODE (scratch2) == SCRATCH)
|| (GET_MODE (scratch2) == SImode
&& REG_P (scratch2)));
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index d5af40f7091..f83e3651a1a 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -1314,7 +1314,7 @@ avr_return_addr_rtx (int count, rtx tem)
/* Can only return this function's return address. Others not supported. */
if (count)
- return NULL;
+ return NULL_RTX;
if (AVR_3_BYTE_PC)
{
diff --git a/gcc/config/bfin/bfin.cc b/gcc/config/bfin/bfin.cc
index 4320ec26722..6219c4c4e39 100644
--- a/gcc/config/bfin/bfin.cc
+++ b/gcc/config/bfin/bfin.cc
@@ -2003,7 +2003,7 @@ bfin_longcall_p (rtx op, int call_cookie)
void
bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
{
- rtx use = NULL, call;
+ rtx use = NULL_RTX, call;
rtx callee = XEXP (fnaddr, 0);
int nelts = 3;
rtx pat;
diff --git a/gcc/config/c6x/c6x.cc b/gcc/config/c6x/c6x.cc
index 0c9cb821f28..2d0e813fb82 100644
--- a/gcc/config/c6x/c6x.cc
+++ b/gcc/config/c6x/c6x.cc
@@ -3730,7 +3730,7 @@ condjump_opposite_condition (rtx insn)
{
rtx pat = PATTERN (insn);
int icode = INSN_CODE (insn);
- rtx x = NULL;
+ rtx x = NULL_RTX;
if (icode == CODE_FOR_br_true || icode == CODE_FOR_br_false)
{
@@ -6302,7 +6302,7 @@ c6x_dwarf_register_span (rtx rtl)
regno = REGNO (rtl);
nregs = REG_NREGS (rtl);
if (nregs == 1)
- return NULL_RTX;
+ return NULL_RTX;
p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc(nregs));
for (i = 0; i < nregs; i++)
diff --git a/gcc/config/csky/csky.cc b/gcc/config/csky/csky.cc
index b4ee3b273a4..db655bb7b23 100644
--- a/gcc/config/csky/csky.cc
+++ b/gcc/config/csky/csky.cc
@@ -1163,7 +1163,7 @@ get_csky_barrier_cost (rtx_insn *insn)
int base_cost = 50;
rtx next = next_nonnote_insn (insn);
- if (next != NULL && GET_CODE (next) == CODE_LABEL)
+ if (next != NULL_RTX && GET_CODE (next) == CODE_LABEL)
base_cost -= 20;
switch (GET_CODE (insn))
diff --git a/gcc/config/darwin.cc b/gcc/config/darwin.cc
index efbcb3856ca..5a3682cbb8c 100644
--- a/gcc/config/darwin.cc
+++ b/gcc/config/darwin.cc
@@ -670,7 +670,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
}
else if (defined && ! MACHO_SYMBOL_MUST_INDIRECT_P (orig))
{
- rtx offset = NULL;
+ rtx offset = NULL_RTX;
if (DARWIN_PPC || HAVE_lo_sum)
offset = machopic_gen_offset (orig);
diff --git a/gcc/config/fr30/fr30.cc b/gcc/config/fr30/fr30.cc
index 0d05b13aa31..58d84a289b6 100644
--- a/gcc/config/fr30/fr30.cc
+++ b/gcc/config/fr30/fr30.cc
@@ -862,7 +862,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
int
fr30_const_double_is_zero (rtx operand)
{
- if (operand == NULL || GET_CODE (operand) != CONST_DOUBLE)
+ if (operand == NULL_RTX || GET_CODE (operand) != CONST_DOUBLE)
return 0;
return real_equal (CONST_DOUBLE_REAL_VALUE (operand), &dconst0);
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 50d9d34ebcb..3f0646bb93c 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -296,7 +296,7 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
/* Don't use integer vector broadcast if we can't move from GPR to SSE
register directly. */
if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
- return nullptr;
+ return NULL_RTX;
/* Convert CONST_WIDE_INT to a non-standard SSE constant integer
broadcast only if vector broadcast is available. */
@@ -305,7 +305,7 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
|| standard_sse_constant_p (op, mode)
|| (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT
!= GET_MODE_BITSIZE (mode)))
- return nullptr;
+ return NULL_RTX;
HOST_WIDE_INT val = CONST_WIDE_INT_ELT (op, 0);
HOST_WIDE_INT val_broadcast;
@@ -326,12 +326,12 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op)
val_broadcast))
broadcast_mode = DImode;
else
- return nullptr;
+ return NULL_RTX;
/* Check if OP can be broadcasted from VAL. */
for (int i = 1; i < CONST_WIDE_INT_NUNITS (op); i++)
if (val != CONST_WIDE_INT_ELT (op, i))
- return nullptr;
+ return NULL_RTX;
unsigned int nunits = (GET_MODE_SIZE (mode)
/ GET_MODE_SIZE (broadcast_mode));
@@ -525,7 +525,7 @@ ix86_expand_move (machine_mode mode, rtx operands[])
{
rtx tmp = ix86_convert_const_wide_int_to_broadcast
(GET_MODE (op0), op1);
- if (tmp != nullptr)
+ if (tmp != NULL_RTX)
op1 = tmp;
}
}
@@ -541,13 +541,13 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
{
int nunits = GET_MODE_NUNITS (mode);
if (nunits < 2)
- return nullptr;
+ return NULL_RTX;
/* Don't use integer vector broadcast if we can't move from GPR to SSE
register directly. */
if (!TARGET_INTER_UNIT_MOVES_TO_VEC
&& INTEGRAL_MODE_P (mode))
- return nullptr;
+ return NULL_RTX;
/* Convert CONST_VECTOR to a non-standard SSE constant integer
broadcast only if vector broadcast is available. */
@@ -557,7 +557,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
|| GET_MODE_INNER (mode) == DImode))
|| FLOAT_MODE_P (mode))
|| standard_sse_constant_p (op, mode))
- return nullptr;
+ return NULL_RTX;
/* Don't broadcast from a 64-bit integer constant in 32-bit mode.
We can still put 64-bit integer constant in memory when
@@ -565,14 +565,14 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
if (GET_MODE_INNER (mode) == DImode && !TARGET_64BIT
&& (!TARGET_AVX512F
|| (GET_MODE_SIZE (mode) < 64 && !TARGET_AVX512VL)))
- return nullptr;
+ return NULL_RTX;
if (GET_MODE_INNER (mode) == TImode)
- return nullptr;
+ return NULL_RTX;
rtx constant = get_pool_constant (XEXP (op, 0));
if (GET_CODE (constant) != CONST_VECTOR)
- return nullptr;
+ return NULL_RTX;
/* There could be some rtx like
(mem/u/c:V16QI (symbol_ref/u:DI ("*.LC1")))
@@ -581,8 +581,8 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
{
constant = simplify_subreg (mode, constant, GET_MODE (constant),
0);
- if (constant == nullptr || GET_CODE (constant) != CONST_VECTOR)
- return nullptr;
+ if (constant == NULL_RTX || GET_CODE (constant) != CONST_VECTOR)
+ return NULL_RTX;
}
rtx first = XVECEXP (constant, 0, 0);
@@ -592,7 +592,7 @@ ix86_broadcast_from_constant (machine_mode mode, rtx op)
rtx tmp = XVECEXP (constant, 0, i);
/* Vector duplicate value. */
if (!rtx_equal_p (tmp, first))
- return nullptr;
+ return NULL_RTX;
}
return first;
@@ -641,7 +641,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
machine_mode mode = GET_MODE (op0);
rtx tmp = ix86_convert_const_wide_int_to_broadcast
(mode, op1);
- if (tmp == nullptr)
+ if (tmp == NULL_RTX)
op1 = validize_mem (force_const_mem (mode, op1));
else
op1 = tmp;
@@ -656,7 +656,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
&& CONSTANT_POOL_ADDRESS_P (XEXP (op1, 0))))
{
rtx first = ix86_broadcast_from_constant (mode, op1);
- if (first != nullptr)
+ if (first != NULL_RTX)
{
/* Broadcast to XMM/YMM/ZMM register from an integer
constant or scalar mem. */
@@ -4655,14 +4655,14 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
case EQ:
/* SSE4.1 supports EQ. */
if (!TARGET_SSE4_1)
- return NULL;
+ return NULL_RTX;
break;
case GT:
case GTU:
/* SSE4.2 supports GT/GTU. */
if (!TARGET_SSE4_2)
- return NULL;
+ return NULL_RTX;
break;
default:
@@ -5797,7 +5797,7 @@ ix86_extract_perm_from_pool_constant (int* perm, rtx mem)
{
constant = simplify_subreg (mode, constant, GET_MODE (constant), 0);
- if (constant == nullptr || GET_CODE (constant) != CONST_VECTOR)
+ if (constant == NULL_RTX || GET_CODE (constant) != CONST_VECTOR)
return false;
}
@@ -5850,7 +5850,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode)
the operand may actually have a different mode now. That's
ok, since we want to pun this all the way back to an integer. */
operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
- gcc_assert (operand != NULL);
+ gcc_assert (operand != NULL_RTX);
mode = imode;
}
@@ -8136,9 +8136,9 @@ expand_set_or_cpymem_constant_prologue (rtx dst, rtx *srcp, rtx destreg,
int desired_align, int align_bytes,
bool issetmem)
{
- rtx src = NULL;
+ rtx src = NULL_RTX;
rtx orig_dst = dst;
- rtx orig_src = NULL;
+ rtx orig_src = NULL_RTX;
int piece_size = 1;
int copied_bytes = 0;
@@ -9388,7 +9388,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
rtx pop, bool sibcall)
{
rtx vec[3];
- rtx use = NULL, call;
+ rtx use = NULL_RTX, call;
unsigned int vec_len = 0;
tree fndecl;
@@ -9404,7 +9404,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
fndecl = NULL_TREE;
if (pop == const0_rtx)
- pop = NULL;
+ pop = NULL_RTX;
gcc_assert (!TARGET_64BIT || !pop);
rtx addr = XEXP (fnaddr, 0);
diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index a0a73486d36..09e14e15be5 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -1812,7 +1812,7 @@ pseudo_reg_set (rtx_insn *insn)
{
rtx set = single_set (insn);
if (!set)
- return NULL;
+ return NULL_RTX;
/* Check pseudo register push first. */
machine_mode mode = TARGET_64BIT ? TImode : DImode;
@@ -1826,11 +1826,11 @@ pseudo_reg_set (rtx_insn *insn)
if (HARD_REGISTER_P (DF_REF_REAL_REG (ref))
&& !DF_REF_FLAGS_IS_SET (ref, DF_REF_MUST_CLOBBER)
&& DF_REF_REGNO (ref) != FLAGS_REG)
- return NULL;
+ return NULL_RTX;
FOR_EACH_INSN_USE (ref, insn)
if (!DF_REF_REG_MEM_P (ref) && HARD_REGISTER_P (DF_REF_REAL_REG (ref)))
- return NULL;
+ return NULL_RTX;
return set;
}
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 6a4b3326219..25590782028 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -2642,12 +2642,12 @@ construct_container (machine_mode mode, machine_mode orig_mode,
n = classify_argument (mode, type, regclass, 0);
if (!n)
- return NULL;
+ return NULL_RTX;
if (examine_argument (mode, type, in_return, &needed_intregs,
&needed_sseregs))
- return NULL;
+ return NULL_RTX;
if (needed_intregs > nintregs || needed_sseregs > nsseregs)
- return NULL;
+ return NULL_RTX;
/* We allowed the user to turn off SSE for kernel mode. Don't crash if
some less clueful developer tries to use floating-point anyway. */
@@ -2656,7 +2656,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
/* Return early if we shouldn't raise an error for invalid
calls. */
if (cfun != NULL && cfun->machine->silent_p)
- return NULL;
+ return NULL_RTX;
if (in_return)
{
if (!issued_sse_ret_error)
@@ -2670,7 +2670,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
error ("SSE register argument with SSE disabled");
issued_sse_arg_error = true;
}
- return NULL;
+ return NULL_RTX;
}
/* Likewise, error if the ABI requires us to return values in the
@@ -2684,13 +2684,13 @@ construct_container (machine_mode mode, machine_mode orig_mode,
/* Return early if we shouldn't raise an error for invalid
calls. */
if (cfun != NULL && cfun->machine->silent_p)
- return NULL;
+ return NULL_RTX;
if (!issued_x87_ret_error)
{
error ("x87 register return with x87 disabled");
issued_x87_ret_error = true;
}
- return NULL;
+ return NULL_RTX;
}
/* First construct simple cases. Avoid SCmode, since we want to use
@@ -2714,7 +2714,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
return gen_rtx_REG (mode, FIRST_STACK_REG);
case X86_64_NO_CLASS:
/* Zero sized array, struct or class. */
- return NULL;
+ return NULL_RTX;
default:
gcc_unreachable ();
}
@@ -2877,7 +2877,7 @@ construct_container (machine_mode mode, machine_mode orig_mode,
/* Empty aligned struct, union or class. */
if (nexps == 0)
- return NULL;
+ return NULL_RTX;
ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
for (i = 0; i < nexps; i++)
@@ -3305,7 +3305,7 @@ function_arg_64 (const CUMULATIVE_ARGS *cum, machine_mode mode,
case E_V8DImode:
/* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
if (!named)
- return NULL;
+ return NULL_RTX;
break;
}
@@ -3756,7 +3756,7 @@ static rtx
zero_all_vector_registers (HARD_REG_SET need_zeroed_hardregs)
{
if (!TARGET_AVX)
- return NULL;
+ return NULL_RTX;
for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if ((LEGACY_SSE_REGNO_P (regno)
@@ -3764,7 +3764,7 @@ zero_all_vector_registers (HARD_REG_SET need_zeroed_hardregs)
&& (REX_SSE_REGNO_P (regno)
|| (TARGET_AVX512F && EXT_REX_SSE_REGNO_P (regno)))))
&& !TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
- return NULL;
+ return NULL_RTX;
return gen_avx_vzeroall ();
}
@@ -4087,7 +4087,7 @@ function_value_64 (machine_mode orig_mode, machine_mode mode,
regno = FIRST_FLOAT_REG;
break;
case E_TCmode:
- return NULL;
+ return NULL_RTX;
default:
regno = AX_REG;
}
@@ -4784,7 +4784,7 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
if (!TARGET_64BIT_MS_ABI)
{
- container = NULL;
+ container = NULL_RTX;
break;
}
/* FALLTHRU */
@@ -5386,7 +5386,7 @@ ix86_standard_x87sse_constant_load_p (const rtx_insn *insn, rtx dst)
gcc_assert (REG_P (dst));
- if (src == NULL
+ if (src == NULL_RTX
|| (SSE_REGNO_P (REGNO (dst))
&& standard_sse_constant_p (src, GET_MODE (dst)) != 1)
|| (STACK_REGNO_P (REGNO (dst))
@@ -7127,7 +7127,7 @@ static rtx
choose_baseaddr (HOST_WIDE_INT cfa_offset, unsigned int *align,
unsigned int scratch_regno = INVALID_REGNUM)
{
- rtx base_reg = NULL;
+ rtx base_reg = NULL_RTX;
HOST_WIDE_INT base_offset = 0;
/* If a specific alignment is requested, try to get a base register
@@ -7138,7 +7138,7 @@ choose_baseaddr (HOST_WIDE_INT cfa_offset, unsigned int *align,
if (!base_reg)
choose_basereg (cfa_offset, base_reg, base_offset, 0, align);
- gcc_assert (base_reg != NULL);
+ gcc_assert (base_reg != NULL_RTX);
rtx base_offset_rtx = GEN_INT (base_offset);
@@ -7574,7 +7574,7 @@ ix86_get_drap_rtx (void)
return drap_vreg;
}
else
- return NULL;
+ return NULL_RTX;
}
/* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
@@ -8843,7 +8843,7 @@ ix86_expand_prologue (void)
else
{
rtx eax = gen_rtx_REG (Pmode, AX_REG);
- rtx r10 = NULL;
+ rtx r10 = NULL_RTX;
const bool sp_is_cfa_reg = (m->fs.cfa_reg == stack_pointer_rtx);
bool eax_live = ix86_eax_live_at_start_p ();
bool r10_live = false;
@@ -11699,7 +11699,7 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
/* Generate DImode references to avoid %fs:(%reg32)
problems and linker IE->LE relaxation bug. */
tp_mode = DImode;
- pic = NULL;
+ pic = NULL_RTX;
type = UNSPEC_GOTNTPOFF;
}
else if (flag_pic)
@@ -11715,7 +11715,7 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
}
else
{
- pic = NULL;
+ pic = NULL_RTX;
type = UNSPEC_INDNTPOFF;
}
diff --git a/gcc/config/i386/winnt.cc b/gcc/config/i386/winnt.cc
index 83a21c67704..007ad430b6c 100644
--- a/gcc/config/i386/winnt.cc
+++ b/gcc/config/i386/winnt.cc
@@ -1280,7 +1280,7 @@ i386_pe_seh_unwind_emit (FILE *out_file, rtx_insn *insn)
case REG_CFA_ADJUST_CFA:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
{
pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL)
@@ -1292,7 +1292,7 @@ i386_pe_seh_unwind_emit (FILE *out_file, rtx_insn *insn)
case REG_CFA_OFFSET:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
pat = single_set (insn);
seh_cfa_offset (out_file, seh, pat);
handled_one = true;
diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc
index 92f34dd1ee7..15a8a9ff788 100644
--- a/gcc/config/ia64/ia64.cc
+++ b/gcc/config/ia64/ia64.cc
@@ -4193,7 +4193,7 @@ rtx
ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
{
if (count != 0)
- return NULL;
+ return NULL_RTX;
return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
}
@@ -10352,7 +10352,7 @@ ia64_asm_unwind_emit (FILE *out_file, rtx_insn *insn)
{
case REG_CFA_ADJUST_CFA:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
pat = PATTERN (insn);
process_cfa_adjust_cfa (out_file, pat, insn, unwind, frame);
handled_one = true;
@@ -10360,7 +10360,7 @@ ia64_asm_unwind_emit (FILE *out_file, rtx_insn *insn)
case REG_CFA_OFFSET:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
pat = PATTERN (insn);
process_cfa_offset (out_file, pat, unwind);
handled_one = true;
@@ -10368,7 +10368,7 @@ ia64_asm_unwind_emit (FILE *out_file, rtx_insn *insn)
case REG_CFA_REGISTER:
pat = XEXP (note, 0);
- if (pat == NULL)
+ if (pat == NULL_RTX)
pat = PATTERN (insn);
process_cfa_register (out_file, pat, unwind);
handled_one = true;
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index eb73d11b869..f7e1bf221de 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -621,7 +621,7 @@ loongarch_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
struct loongarch_arg_info info;
if (arg.end_marker_p ())
- return NULL;
+ return NULL_RTX;
return loongarch_get_arg_info (&info, cum, arg.mode, arg.type, arg.named,
false);
@@ -2853,9 +2853,9 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
|| !loongarch_split_symbol_type (symbol_type))
return false;
- rtx high, temp1 = NULL;
+ rtx high, temp1 = NULL_RTX;
- if (temp == NULL)
+ if (temp == NULL_RTX)
temp = gen_reg_rtx (Pmode);
/* Get the 12-31 bits of the address. */
@@ -4650,7 +4650,7 @@ loongarch_expand_atomic_qihi (union loongarch_gen_fn_ptrs generator,
{
rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
rtx unshifted_mask_reg, mask, inverted_mask, si_op;
- rtx res = NULL;
+ rtx res = NULL_RTX;
machine_mode mode;
mode = GET_MODE (mem);
diff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc
index 03db2b6a936..8b2d327f3d2 100644
--- a/gcc/config/m68k/m68k.cc
+++ b/gcc/config/m68k/m68k.cc
@@ -2411,7 +2411,7 @@ m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
UNSPEC_RELOC32);
x = gen_rtx_CONST (Pmode, x);
- if (temp_reg == NULL)
+ if (temp_reg == NULL_RTX)
{
gcc_assert (can_create_pseudo_p ());
temp_reg = gen_reg_rtx (Pmode);
@@ -4079,7 +4079,7 @@ m68k_movem_pattern_p (rtx pattern, rtx automod_base,
enum reg_class rclass;
len = XVECLEN (pattern, 0);
- first = (automod_base != NULL);
+ first = (automod_base != NULL_RTX);
if (automod_base)
{
@@ -4094,11 +4094,11 @@ m68k_movem_pattern_p (rtx pattern, rtx automod_base,
else
{
/* Allow any valid base and offset in the first access. */
- base = NULL;
+ base = NULL_RTX;
offset = 0;
}
- last_reg = NULL;
+ last_reg = NULL_RTX;
rclass = NO_REGS;
for (i = first; i < len; i++)
{
@@ -4113,7 +4113,7 @@ m68k_movem_pattern_p (rtx pattern, rtx automod_base,
return false;
/* ...with the right address. */
- if (base == NULL)
+ if (base == NULL_RTX)
{
m68k_split_offset (XEXP (mem, 0), &base, &offset);
/* The ColdFire instruction only allows (An) and (d16,An) modes.
@@ -6005,7 +6005,7 @@ sched_get_operand (rtx_insn *insn, bool opx_p)
i = get_attr_opy (insn);
if (i >= recog_data.n_operands)
- return NULL;
+ return NULL_RTX;
return recog_data.operand[i];
}
@@ -6019,7 +6019,7 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
op = sched_get_operand (insn, opx_p);
- if (op == NULL)
+ if (op == NULL_RTX)
{
gcc_assert (!reload_completed);
return OP_TYPE_RN;
@@ -6866,17 +6866,17 @@ m68k_sched_dfa_post_advance_cycle (void)
static rtx
sched_get_reg_operand (rtx_insn *insn, bool opx_p)
{
- rtx op = NULL;
+ rtx op = NULL_RTX;
if (opx_p)
{
if (get_attr_opx_type (insn) == OPX_TYPE_RN)
{
op = sched_get_operand (insn, true);
- gcc_assert (op != NULL);
+ gcc_assert (op != NULL_RTX);
if (!reload_completed && !REG_P (op))
- return NULL;
+ return NULL_RTX;
}
}
else
@@ -6884,10 +6884,10 @@ sched_get_reg_operand (rtx_insn *insn, bool opx_p)
if (get_attr_opy_type (insn) == OPY_TYPE_RN)
{
op = sched_get_operand (insn, false);
- gcc_assert (op != NULL);
+ gcc_assert (op != NULL_RTX);
if (!reload_completed && !REG_P (op))
- return NULL;
+ return NULL_RTX;
}
}
@@ -6940,7 +6940,7 @@ sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p)
return sched_get_operand (insn, true);
gcc_unreachable ();
- return NULL;
+ return NULL_RTX;
}
/* Return non-zero if PRO modifies register used as part of
@@ -6952,11 +6952,11 @@ m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con)
rtx con_mem_read;
pro_x = sched_get_reg_operand (pro, true);
- if (pro_x == NULL)
+ if (pro_x == NULL_RTX)
return 0;
con_mem_read = sched_get_mem_operand (con, true, false);
- gcc_assert (con_mem_read != NULL);
+ gcc_assert (con_mem_read != NULL_RTX);
if (reg_mentioned_p (pro_x, con_mem_read))
return 1;
@@ -6975,11 +6975,11 @@ sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con)
struct m68k_address address;
reg = sched_get_reg_operand (pro, true);
- if (reg == NULL)
+ if (reg == NULL_RTX)
return 0;
mem = sched_get_mem_operand (con, true, false);
- gcc_assert (mem != NULL && MEM_P (mem));
+ gcc_assert (mem != NULL_RTX && MEM_P (mem));
if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
&address))
diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
index cbabf1af712..ee3db97dc63 100644
--- a/gcc/config/microblaze/microblaze.cc
+++ b/gcc/config/microblaze/microblaze.cc
@@ -744,7 +744,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
info->offset = NULL;
info->symbol = NULL;
info->symbol_type = SYMBOL_TYPE_INVALID;
- offset = NULL;
+ offset = NULL_RTX;
switch (GET_CODE (x))
{
@@ -1103,7 +1103,7 @@ microblaze_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (xinsn) == SYMBOL_REF)
{
- rtx reg = NULL;
+ rtx reg = NULL_RTX;
if (microblaze_tls_symbol_p(xinsn))
{
reg = microblaze_legitimize_tls_address (xinsn, NULL_RTX);
@@ -3418,7 +3418,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
}
if (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1,1)) == CONST)
{
- rtx p0, p1 = NULL, result, temp;
+ rtx p0, p1 = NULL_RTX, result, temp;
p0 = XEXP (XEXP (op1,1), 0);
@@ -3429,7 +3429,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
}
/* This should never happen. */
- if (p1 == NULL)
+ if (p1 == NULL_RTX)
gcc_unreachable ();
if (GET_CODE (p0) == UNSPEC && GET_CODE (p1) == CONST_INT
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca491b981a3..fe43c1a1494 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -3305,8 +3305,8 @@ mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
/* If we used the temporary register to load $gp, we can't use
it for the high part as well. */
- if (temp != NULL && reg_overlap_mentioned_p (base, temp))
- temp = NULL;
+ if (temp != NULL_RTX && reg_overlap_mentioned_p (base, temp))
+ temp = NULL_RTX;
high = mips_unspec_offset_high (temp, base, addr, type);
lo_sum_symbol = mips_unspec_address (addr, type);
@@ -5993,14 +5993,14 @@ mips_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
if (TARGET_MIPS16 && cum->fp_code != 0)
return gen_rtx_REG ((machine_mode) cum->fp_code, 0);
else
- return NULL;
+ return NULL_RTX;
}
mips_get_arg_info (&info, cum, arg.mode, arg.type, arg.named);
/* Return straight away if the whole argument is passed on the stack. */
if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
- return NULL;
+ return NULL_RTX;
/* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
contains a double in its entirety, then that 64-bit chunk is passed
@@ -8394,7 +8394,7 @@ mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
{
rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
rtx unshifted_mask_reg, mask, inverted_mask, si_op;
- rtx res = NULL;
+ rtx res = NULL_RTX;
machine_mode mode;
mode = GET_MODE (mem);
diff --git a/gcc/config/mn10300/mn10300.cc b/gcc/config/mn10300/mn10300.cc
index a8b01a543cc..d040eaa825e 100644
--- a/gcc/config/mn10300/mn10300.cc
+++ b/gcc/config/mn10300/mn10300.cc
@@ -1419,7 +1419,7 @@ mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
&& (rclass == FP_REGS || xclass == FP_REGS)
&& (xclass == NO_REGS || rclass == NO_REGS))
{
- rtx addr = NULL;
+ rtx addr = NULL_RTX;
if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM)
{
@@ -1850,7 +1850,7 @@ mn10300_legitimize_pic_address (rtx orig, rtx reg)
&& (CONSTANT_POOL_ADDRESS_P (orig)
|| ! MN10300_GLOBAL_P (orig))))
{
- if (reg == NULL)
+ if (reg == NULL_RTX)
reg = gen_reg_rtx (Pmode);
x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF);
@@ -1861,7 +1861,7 @@ mn10300_legitimize_pic_address (rtx orig, rtx reg)
}
else if (GET_CODE (orig) == SYMBOL_REF)
{
- if (reg == NULL)
+ if (reg == NULL_RTX)
reg = gen_reg_rtx (Pmode);
x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT);
@@ -2083,7 +2083,7 @@ mn10300_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
static rtx
mn10300_delegitimize_address (rtx orig_x)
{
- rtx x = orig_x, ret, addend = NULL;
+ rtx x = orig_x, ret, addend = NULL_RTX;
bool need_mem;
if (MEM_P (x))
diff --git a/gcc/config/msp430/msp430.cc b/gcc/config/msp430/msp430.cc
index 6f9c56187ee..d955e71adb4 100644
--- a/gcc/config/msp430/msp430.cc
+++ b/gcc/config/msp430/msp430.cc
@@ -3323,7 +3323,7 @@ msp430_expand_helper (rtx *operands, const char *helper_name,
RTL_CONST_CALL_P (c) = 1;
/* Add register usage information for the arguments to the call. */
- fusage = NULL;
+ fusage = NULL_RTX;
use_regs (&fusage, arg1, arg1sz);
if (!helper_const)
{
diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc
index d76c0bbce2f..8fca887ef39 100644
--- a/gcc/config/nvptx/nvptx.cc
+++ b/gcc/config/nvptx/nvptx.cc
@@ -2692,7 +2692,7 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee)
tree decl = NULL_TREE;
fprintf (asm_out_file, "\t{\n");
- if (result != NULL)
+ if (result != NULL_RTX)
fprintf (asm_out_file, "\t\t.param%s %s_in;\n",
nvptx_ptx_type_from_mode (GET_MODE (result), false),
reg_names[NVPTX_RETURN_REGNUM]);
diff --git a/gcc/config/or1k/or1k.cc b/gcc/config/or1k/or1k.cc
index ec30bc8156c..aa5a199dc8c 100644
--- a/gcc/config/or1k/or1k.cc
+++ b/gcc/config/or1k/or1k.cc
@@ -324,7 +324,7 @@ void
or1k_expand_epilogue (void)
{
HOST_WIDE_INT reg_offset, sp_offset;
- rtx insn, cfa_restores = NULL;
+ rtx insn, cfa_restores = NULL_RTX;
sp_offset = cfun->machine->total_size;
if (sp_offset == 0)
@@ -1530,7 +1530,7 @@ or1k_expand_compare (rtx *operands)
void
or1k_expand_call (rtx retval, rtx fnaddr, rtx callarg1, bool sibcall)
{
- rtx call, use = NULL;
+ rtx call, use = NULL_RTX;
/* Calls via the PLT require the PIC register. */
if (flag_pic
diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index 0fa9e5fd632..63f0a351e2b 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -2303,7 +2303,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
else if (tls_referenced_p (operand1))
{
rtx tmp = operand1;
- rtx addend = NULL;
+ rtx addend = NULL_RTX;
if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
{
diff --git a/gcc/config/pdp11/pdp11.cc b/gcc/config/pdp11/pdp11.cc
index f6dd841f184..bdfe30b3171 100644
--- a/gcc/config/pdp11/pdp11.cc
+++ b/gcc/config/pdp11/pdp11.cc
@@ -329,7 +329,7 @@ pdp11_expand_prologue (void)
{
HOST_WIDE_INT fsize = get_frame_size ();
unsigned regno;
- rtx x, via_ac = NULL;
+ rtx x, via_ac = NULL_RTX;
/* If we are outputting code for main, the switch FPU to the
right mode if TARGET_FPU. */
@@ -362,7 +362,7 @@ pdp11_expand_prologue (void)
for (regno = AC4_REGNUM; regno <= AC5_REGNUM; regno++)
if (pdp11_saved_regno (regno))
{
- gcc_assert (via_ac != NULL);
+ gcc_assert (via_ac != NULL_RTX);
emit_move_insn (via_ac, gen_rtx_REG (DFmode, regno));
x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
@@ -390,7 +390,7 @@ pdp11_expand_epilogue (void)
{
HOST_WIDE_INT fsize = get_frame_size ();
unsigned regno;
- rtx x, reg, via_ac = NULL;
+ rtx x, reg, via_ac = NULL_RTX;
/* Deallocate the local variables. */
if (fsize)
diff --git a/gcc/config/riscv/riscv-sr.cc b/gcc/config/riscv/riscv-sr.cc
index 7248f04d68f..0eacbd52dc0 100644
--- a/gcc/config/riscv/riscv-sr.cc
+++ b/gcc/config/riscv/riscv-sr.cc
@@ -404,9 +404,9 @@ riscv_remove_unneeded_save_restore_calls (void)
gcc_assert (GET_CODE (callpat) == PARALLEL);
/* Extract from CALLPAT the information we need to build the sibcall. */
- rtx target_call = NULL;
+ rtx target_call = NULL_RTX;
rtx tmp_rtx = XVECEXP (callpat, 0, 0);
- rtx set_target = NULL;
+ rtx set_target = NULL_RTX;
switch (GET_CODE (tmp_rtx))
{
case CALL:
@@ -447,8 +447,8 @@ riscv_remove_unneeded_save_restore_calls (void)
&& !SIBCALL_REG_P (REGNO (target)))
return;
- rtx sibcall = NULL;
- if (set_target != NULL)
+ rtx sibcall = NULL_RTX;
+ if (set_target != NULL_RTX)
sibcall
= gen_sibcall_value_internal (set_target, target, const0_rtx);
else
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2a7b43849e5..8ef4e320463 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1579,7 +1579,7 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
if (! nonzero_address_p (addr))
SYMBOL_REF_WEAK (label) = 1;
- if (temp == NULL)
+ if (temp == NULL_RTX)
temp = gen_reg_rtx (Pmode);
if (Pmode == DImode)
@@ -3935,7 +3935,7 @@ riscv_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
struct riscv_arg_info info;
if (arg.end_marker_p ())
- return NULL;
+ return NULL_RTX;
return riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
}
diff --git a/gcc/config/rl78/rl78.cc b/gcc/config/rl78/rl78.cc
index 9083096c4ae..ec36b593c8a 100644
--- a/gcc/config/rl78/rl78.cc
+++ b/gcc/config/rl78/rl78.cc
@@ -625,7 +625,7 @@ int
rl78_force_nonfar_2 (rtx *operands, rtx (*gen)(rtx,rtx))
{
int did = 0;
- rtx temp_reg = NULL;
+ rtx temp_reg = NULL_RTX;
/* FIXME: in the future, be smarter about only doing this if the
other operand is also far, assuming the devirtualizer can also
@@ -650,7 +650,7 @@ int
rl78_force_nonfar_3 (rtx *operands, rtx (*gen)(rtx,rtx,rtx))
{
int did = 0;
- rtx temp_reg = NULL;
+ rtx temp_reg = NULL_RTX;
/* FIXME: Likewise. */
if (rl78_far_p (operands[1]))
@@ -678,13 +678,13 @@ rl78_force_nonfar_3 (rtx *operands, rtx (*gen)(rtx,rtx,rtx))
int
rl78_one_far_p (rtx *operands, int n)
{
- rtx which = NULL;
+ rtx which = NULL_RTX;
int i, c = 0;
for (i = 0; i < n; i ++)
if (rl78_far_p (operands[i]))
{
- if (which == NULL)
+ if (which == NULL_RTX)
which = operands[i];
else if (rtx_equal_p (operands[i], which))
continue;
@@ -4285,7 +4285,7 @@ rl78_remove_unused_sets (void)
ninsn = next_nonnote_nondebug_insn (insn);
rtx set = single_set (insn);
- if (set == NULL)
+ if (set == NULL_RTX)
continue;
dest = SET_DEST (set);
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index 5384c10b986..914d20e73de 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -2078,7 +2078,7 @@ rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
/* If there is no incoming register, we need a stack. */
entry_parm = rs6000_function_arg (args_so_far, arg);
- if (entry_parm == NULL)
+ if (entry_parm == NULL_RTX)
return true;
/* Likewise if we need to pass both in registers and on the stack. */
diff --git a/gcc/config/rs6000/rs6000-logue.cc b/gcc/config/rs6000/rs6000-logue.cc
index bc6b153b59f..cd6a0cc5bfb 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -2351,7 +2351,7 @@ rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
- if (sym == NULL)
+ if (sym == NULL_RTX)
{
char *name;
@@ -3663,7 +3663,7 @@ rs6000_emit_prologue (void)
if (!WORLD_SAVE_P (info) && info->push_p
&& !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
{
- rtx ptr_reg = NULL;
+ rtx ptr_reg = NULL_RTX;
int ptr_off = 0;
/* If saving altivec regs we need to be able to address all save
diff --git a/gcc/config/rs6000/rs6000-pcrel-opt.cc b/gcc/config/rs6000/rs6000-pcrel-opt.cc
index 4ae16e6bf88..aef4b780e29 100644
--- a/gcc/config/rs6000/rs6000-pcrel-opt.cc
+++ b/gcc/config/rs6000/rs6000-pcrel-opt.cc
@@ -548,7 +548,7 @@ get_mem_base_reg (rtx mem)
if (fmt[0] != 'e')
return NULL_RTX;
mem = XEXP (mem, 0);
- if (mem == NULL_RTX )
+ if (mem == NULL_RTX)
return NULL_RTX;
}
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 9284477396d..34f6d5f1973 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -12358,7 +12358,7 @@ s390_output_split_stack_data (rtx parm_block, rtx call_done,
void
s390_expand_split_stack_prologue (void)
{
- rtx r1, guard, cc = NULL;
+ rtx r1, guard, cc = NULL_RTX;
rtx_insn *insn;
/* Offset from thread pointer to __private_ss. */
int psso = TARGET_64BIT ? 0x38 : 0x20;
@@ -12440,7 +12440,7 @@ s390_expand_split_stack_prologue (void)
/* Now, we need to call __morestack. It has very special calling
conventions: it preserves param/return/static chain registers for
calling main function body, and looks for its own parameters at %r1. */
- if (cc != NULL)
+ if (cc != NULL_RTX)
tmp = gen_split_stack_cond_call (Pmode,
morestack_ref,
parm_base,
@@ -12461,7 +12461,7 @@ s390_expand_split_stack_prologue (void)
add_reg_note (insn, REG_LABEL_OPERAND, parm_base);
add_reg_note (insn, REG_LABEL_OPERAND, call_done);
- if (cc != NULL)
+ if (cc != NULL_RTX)
{
/* Mark the jump as very unlikely to be taken. */
add_reg_br_prob_note (insn,
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 938f7aa6281..3d50440f3d1 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -11617,14 +11617,14 @@ sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0,
/* Find the def of the reg and trace it. If there are more than one
defs and they are not the same, assume it's not safe to proceed. */
rtx_insn* last_i = NULL;
- rtx last_set = NULL;
+ rtx last_set = NULL_RTX;
for (df_ref d = DF_REG_DEF_CHAIN (REGNO (x)); d != NULL;
d = DF_REF_NEXT_REG (d))
{
rtx set = const_cast<rtx> (set_of (x, DF_REF_INSN (d)));
/* Accept multiple defs, as long as they are equal. */
- if (last_set == NULL || rtx_equal_p (last_set, set))
+ if (last_set == NULL_RTX || rtx_equal_p (last_set, set))
{
last_i = DF_REF_INSN (d);
last_set = set;
@@ -11632,12 +11632,12 @@ sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0,
else
{
last_i = NULL;
- last_set = NULL;
+ last_set = NULL_RTX;
break;
}
}
- if (last_set != NULL && last_i != NULL)
+ if (last_set != NULL_RTX && last_i != NULL)
return sh_find_base_reg_disp (last_i, XEXP (last_set, 1), disp,
XEXP (last_set, 0));
@@ -12004,7 +12004,7 @@ sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[])
sh_extending_set_of_reg
sh_find_extending_set_of_reg (rtx reg, rtx_insn* curr_insn)
{
- if (reg == NULL)
+ if (reg == NULL_RTX)
return sh_extending_set_of_reg (curr_insn);
if (SUBREG_P (reg))
diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc
index 9f6a89fa71f..5cffa6148f8 100644
--- a/gcc/config/sh/sh_treg_combine.cc
+++ b/gcc/config/sh/sh_treg_combine.cc
@@ -917,11 +917,11 @@ sh_treg_combine::make_not_reg_insn (rtx dst_reg, rtx src_reg) const
{
// On SH we can do only SImode and DImode comparisons.
if (! (GET_MODE (src_reg) == SImode || GET_MODE (src_reg) == DImode))
- return NULL;
+ return NULL_RTX;
// On SH we can store the ccreg into an SImode or DImode reg only.
if (! (GET_MODE (dst_reg) == SImode || GET_MODE (dst_reg) == DImode))
- return NULL;
+ return NULL_RTX;
start_sequence ();
diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 0aade05faf5..9d538484026 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -3692,7 +3692,7 @@ gen_df_reg (rtx reg, int low)
static void
emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
{
- rtx ret_slot = NULL, arg[3], func_sym;
+ rtx ret_slot = NULL_RTX, arg[3], func_sym;
int i;
/* We only expect to be called for conversions, unary, and binary ops. */
@@ -4531,7 +4531,7 @@ sparc_pic_register_p (rtx x)
static bool
sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
{
- rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
+ rtx rs1 = NULL_RTX, rs2 = NULL_RTX, imm1 = NULL_RTX;
if (REG_P (addr) || GET_CODE (addr) == SUBREG)
rs1 = addr;
@@ -4566,7 +4566,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& RTX_OK_FOR_OFFSET_P (rs2, mode)))
{
imm1 = rs2;
- rs2 = NULL;
+ rs2 = NULL_RTX;
}
else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
&& (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
@@ -4599,7 +4599,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& ! TARGET_CM_MEDMID
&& RTX_OK_FOR_OLO10_P (rs2, mode))
{
- rs2 = NULL;
+ rs2 = NULL_RTX;
imm1 = XEXP (rs1, 1);
rs1 = XEXP (rs1, 0);
if (!CONSTANT_P (imm1)
diff --git a/gcc/config/stormy16/stormy16.cc b/gcc/config/stormy16/stormy16.cc
index cd453c2a2f7..f7e6b56983f 100644
--- a/gcc/config/stormy16/stormy16.cc
+++ b/gcc/config/stormy16/stormy16.cc
@@ -2082,7 +2082,7 @@ xstormy16_expand_call (rtx retval, rtx dest, rtx counter)
if (! CONSTANT_P (dest) && ! REG_P (dest))
dest = force_reg (Pmode, dest);
- if (retval == NULL)
+ if (retval == NULL_RTX)
mode = VOIDmode;
else
mode = GET_MODE (retval);
diff --git a/gcc/config/visium/visium.cc b/gcc/config/visium/visium.cc
index 48a61744db6..b0b8485ff55 100644
--- a/gcc/config/visium/visium.cc
+++ b/gcc/config/visium/visium.cc
@@ -1148,7 +1148,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
{
rtx dest = SET_DEST (set);
const bool double_p = GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD;
- rtx memrtx = NULL;
+ rtx memrtx = NULL_RTX;
if (GET_CODE (SET_SRC (set)) == MEM)
{
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index bb1444c44b6..b5e00761035 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -1215,7 +1215,7 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
if (xtensa_tls_referenced_p (src))
{
- rtx addend = NULL;
+ rtx addend = NULL_RTX;
if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
{
diff --git a/gcc/cprop.cc b/gcc/cprop.cc
index 6ec0bda4a24..97e8001ab70 100644
--- a/gcc/cprop.cc
+++ b/gcc/cprop.cc
@@ -1059,7 +1059,7 @@ cprop_insn (rtx_insn *insn)
{
rtx reg_used = reg_use_table[i];
unsigned int regno = REGNO (reg_used);
- rtx src_cst = NULL, src_reg = NULL;
+ rtx src_cst = NULL_RTX, src_reg = NULL_RTX;
struct cprop_expr *set[2];
/* If the register has already been set in this block, there's
@@ -1174,7 +1174,7 @@ local_cprop_find_used_regs (rtx *xptr, void *data)
static bool
do_local_cprop (rtx x, rtx_insn *insn)
{
- rtx newreg = NULL, newcnst = NULL;
+ rtx newreg = NULL_RTX, newcnst = NULL_RTX;
/* Rule out USE instructions and ASM statements as we don't want to
change the hard registers mentioned. */
diff --git a/gcc/cse.cc b/gcc/cse.cc
index 86403b95938..a2bac15db00 100644
--- a/gcc/cse.cc
+++ b/gcc/cse.cc
@@ -2904,7 +2904,7 @@ find_comparison_args (enum rtx_code code, rtx *parg1, rtx *parg2,
rtx arg1, arg2;
hash_set<rtx> *visited = NULL;
/* Set nonzero when we find something of interest. */
- rtx x = NULL;
+ rtx x = NULL_RTX;
arg1 = *parg1, arg2 = *parg2;
diff --git a/gcc/cselib.cc b/gcc/cselib.cc
index 065867b4a84..cc039a27245 100644
--- a/gcc/cselib.cc
+++ b/gcc/cselib.cc
@@ -139,7 +139,7 @@ cselib_hasher::equal (const cselib_val *v, const key *x_arg)
if (SP_DERIVED_VALUE_P (v->val_rtx) && GET_MODE (x) == Pmode)
{
- rtx xoff = NULL;
+ rtx xoff = NULL_RTX;
if (autoinc_split (x, &xoff, memmode) == v->val_rtx && xoff == NULL_RTX)
return true;
}
@@ -970,7 +970,7 @@ rtx_equal_for_cselib_1 (rtx x, rtx y, machine_mode memmode, int depth)
|| SP_DERIVED_VALUE_P (e->val_rtx))
&& GET_MODE (y) == Pmode)
{
- rtx yoff = NULL;
+ rtx yoff = NULL_RTX;
rtx yr = autoinc_split (y, &yoff, memmode);
if ((yr == x || yr == e->val_rtx) && yoff == NULL_RTX)
return 1;
@@ -1003,7 +1003,7 @@ rtx_equal_for_cselib_1 (rtx x, rtx y, machine_mode memmode, int depth)
|| SP_DERIVED_VALUE_P (e->val_rtx))
&& GET_MODE (x) == Pmode)
{
- rtx xoff = NULL;
+ rtx xoff = NULL_RTX;
rtx xr = autoinc_split (x, &xoff, memmode);
if ((xr == y || xr == e->val_rtx) && xoff == NULL_RTX)
return 1;
@@ -1035,7 +1035,7 @@ rtx_equal_for_cselib_1 (rtx x, rtx y, machine_mode memmode, int depth)
&& CONST_INT_P (XEXP (y, 1))))
{
rtx xorig = x, yorig = y;
- rtx xoff = NULL, yoff = NULL;
+ rtx xoff = NULL_RTX, yoff = NULL_RTX;
x = autoinc_split (x, &xoff, memmode);
y = autoinc_split (y, &yoff, memmode);
@@ -1709,7 +1709,7 @@ static rtx
expand_loc (struct elt_loc_list *p, struct expand_value_data *evd,
int max_depth)
{
- rtx reg_result = NULL;
+ rtx reg_result = NULL_RTX;
unsigned int regno = UINT_MAX;
struct elt_loc_list *p_in = p;
diff --git a/gcc/df-core.cc b/gcc/df-core.cc
index d4812b04a7c..c7d1e31f3f9 100644
--- a/gcc/df-core.cc
+++ b/gcc/df-core.cc
@@ -2045,7 +2045,7 @@ df_find_single_def_src (rtx reg)
return NULL_RTX;
rtx set = single_set (DF_REF_INSN (adef));
- if (set == NULL || !rtx_equal_p (SET_DEST (set), reg))
+ if (set == NULL_RTX || !rtx_equal_p (SET_DEST (set), reg))
return NULL_RTX;
rtx note = find_reg_equal_equiv_note (DF_REF_INSN (adef));
diff --git a/gcc/dse.cc b/gcc/dse.cc
index 802b949cfb2..ff6ac7a8e0a 100644
--- a/gcc/dse.cc
+++ b/gcc/dse.cc
@@ -1513,7 +1513,7 @@ record_store (rtx body, bb_info_t bb_info)
/* If RHS is set only once to a constant, set CONST_RHS
to the constant. */
rtx def_src = df_find_single_def_src (rhs);
- if (def_src != nullptr && CONSTANT_P (def_src))
+ if (def_src != NULL_RTX && CONSTANT_P (def_src))
const_rhs = def_src;
}
}
@@ -1721,7 +1721,7 @@ find_shift_sequence (poly_int64 access_size,
{
machine_mode store_mode = GET_MODE (store_info->mem);
scalar_int_mode new_mode;
- rtx read_reg = NULL;
+ rtx read_reg = NULL_RTX;
/* If a constant was stored into memory, try to simplify it here,
otherwise the cost of the shift might preclude this optimization
diff --git a/gcc/dwarf2cfi.cc b/gcc/dwarf2cfi.cc
index 57283c10a29..fc917faedd5 100644
--- a/gcc/dwarf2cfi.cc
+++ b/gcc/dwarf2cfi.cc
@@ -1045,7 +1045,7 @@ notice_args_size (rtx_insn *insn)
rtx note;
note = find_reg_note (insn, REG_ARGS_SIZE, NULL);
- if (note == NULL)
+ if (note == NULL_RTX)
return;
if (!cur_trace->eh_head)
@@ -1189,14 +1189,14 @@ record_reg_saved_in_reg (rtx dest, rtx src)
FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt)
if (compare_reg_or_pc (elt->orig_reg, src))
{
- if (dest == NULL)
+ if (dest == NULL_RTX)
cur_trace->regs_saved_in_regs.unordered_remove (i);
else
elt->saved_in_reg = dest;
return;
}
- if (dest == NULL)
+ if (dest == NULL_RTX)
return;
reg_saved_in_data e = {src, dest};
@@ -1382,7 +1382,7 @@ dwarf2out_frame_debug_cfa_offset (rtx set)
if (src == pc_rtx)
{
- span = NULL;
+ span = NULL_RTX;
sregno = DWARF_FRAME_RETURN_COLUMN;
}
else
@@ -2207,7 +2207,7 @@ dwarf2out_frame_debug_expr (rtx expr)
if (REG_P (src))
span = targetm.dwarf_register_span (src);
else
- span = NULL;
+ span = NULL_RTX;
if (!span)
{
@@ -2268,7 +2268,7 @@ dwarf2out_frame_debug (rtx_insn *insn)
case REG_CFA_ADJUST_CFA:
n = XEXP (note, 0);
- if (n == NULL)
+ if (n == NULL_RTX)
{
n = PATTERN (insn);
if (GET_CODE (n) == PARALLEL)
@@ -2280,7 +2280,7 @@ dwarf2out_frame_debug (rtx_insn *insn)
case REG_CFA_OFFSET:
n = XEXP (note, 0);
- if (n == NULL)
+ if (n == NULL_RTX)
n = single_set (insn);
dwarf2out_frame_debug_cfa_offset (n);
handled_one = true;
@@ -2288,7 +2288,7 @@ dwarf2out_frame_debug (rtx_insn *insn)
case REG_CFA_REGISTER:
n = XEXP (note, 0);
- if (n == NULL)
+ if (n == NULL_RTX)
{
n = PATTERN (insn);
if (GET_CODE (n) == PARALLEL)
@@ -2301,7 +2301,7 @@ dwarf2out_frame_debug (rtx_insn *insn)
case REG_CFA_EXPRESSION:
case REG_CFA_VAL_EXPRESSION:
n = XEXP (note, 0);
- if (n == NULL)
+ if (n == NULL_RTX)
n = single_set (insn);
if (REG_NOTE_KIND (note) == REG_CFA_EXPRESSION)
@@ -2315,7 +2315,7 @@ dwarf2out_frame_debug (rtx_insn *insn)
case REG_CFA_RESTORE:
case REG_CFA_NO_RESTORE:
n = XEXP (note, 0);
- if (n == NULL)
+ if (n == NULL_RTX)
{
n = PATTERN (insn);
if (GET_CODE (n) == PARALLEL)
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index d89ffa66847..4a348d27679 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -764,7 +764,7 @@ output_call_frame_info (int for_eh)
int per_encoding = DW_EH_PE_absptr;
int lsda_encoding = DW_EH_PE_absptr;
int return_reg;
- rtx personality = NULL;
+ rtx personality = NULL_RTX;
int dw_cie_version;
/* Don't emit a CIE if there won't be any FDEs. */
diff --git a/gcc/explow.cc b/gcc/explow.cc
index 6424c0802f0..682fb597e56 100644
--- a/gcc/explow.cc
+++ b/gcc/explow.cc
@@ -955,7 +955,7 @@ adjust_stack_1 (rtx adjust, bool anti_p)
{
insn = get_last_insn ();
temp = single_set (insn);
- gcc_assert (temp != NULL && SET_DEST (temp) == stack_pointer_rtx);
+ gcc_assert (temp != NULL_RTX && SET_DEST (temp) == stack_pointer_rtx);
}
if (!suppress_reg_args_size)
diff --git a/gcc/expr.cc b/gcc/expr.cc
index 5ede094e705..4d5e12e1d08 100644
--- a/gcc/expr.cc
+++ b/gcc/expr.cc
@@ -2736,7 +2736,7 @@ emit_group_load (rtx dst, rtx src, tree type, poly_int64 ssize)
for (i = 0; i < XVECLEN (dst, 0); i++)
{
rtx d = XEXP (XVECEXP (dst, 0, i), 0);
- if (d == NULL)
+ if (d == NULL_RTX)
continue;
emit_move_insn (d, tmps[i]);
}
@@ -3469,26 +3469,26 @@ clear_storage_hints (rtx object, rtx size, enum block_op_methods method,
&& known_eq (size_val, GET_MODE_SIZE (mode)))
{
rtx zero = CONST0_RTX (mode);
- if (zero != NULL)
+ if (zero != NULL_RTX)
{
emit_move_insn (object, zero);
- return NULL;
+ return NULL_RTX;
}
if (COMPLEX_MODE_P (mode))
{
zero = CONST0_RTX (GET_MODE_INNER (mode));
- if (zero != NULL)
+ if (zero != NULL_RTX)
{
write_complex_part (object, zero, 0, true);
write_complex_part (object, zero, 1, false);
- return NULL;
+ return NULL_RTX;
}
}
}
if (size == const0_rtx)
- return NULL;
+ return NULL_RTX;
align = MEM_ALIGN (object);
@@ -3511,7 +3511,7 @@ clear_storage_hints (rtx object, rtx size, enum block_op_methods method,
else
gcc_unreachable ();
- return NULL;
+ return NULL_RTX;
}
rtx
@@ -4515,7 +4515,7 @@ mem_autoinc_base (rtx mem)
if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
return XEXP (addr, 0);
}
- return NULL;
+ return NULL_RTX;
}
/* A utility routine used here, in reload, and in try_split. The insns
@@ -4545,7 +4545,7 @@ find_args_size_adjust (rtx_insn *insn)
int i;
pat = PATTERN (insn);
- set = NULL;
+ set = NULL_RTX;
/* Look for a call_pop pattern. */
if (CALL_P (insn))
@@ -13409,7 +13409,7 @@ get_personality_function (tree decl)
pk = function_needs_eh_personality (DECL_STRUCT_FUNCTION (decl));
if (pk == eh_personality_none)
- return NULL;
+ return NULL_RTX;
if (!personality
&& pk == eh_personality_any)
diff --git a/gcc/final.cc b/gcc/final.cc
index e614491a69a..e697e8e6f94 100644
--- a/gcc/final.cc
+++ b/gcc/final.cc
@@ -1806,7 +1806,7 @@ profile_function (FILE *file ATTRIBUTE_UNUSED)
# define NO_PROFILE_COUNTERS 0
#endif
#ifdef ASM_OUTPUT_REG_PUSH
- rtx sval = NULL, chain = NULL;
+ rtx sval = NULL_RTX, chain = NULL_RTX;
if (cfun->returns_struct)
sval = targetm.calls.struct_value_rtx (TREE_TYPE (current_function_decl),
diff --git a/gcc/function.cc b/gcc/function.cc
index f0ae641512d..f587439d85b 100644
--- a/gcc/function.cc
+++ b/gcc/function.cc
@@ -1700,7 +1700,7 @@ instantiate_virtual_regs_in_insn (rtx_insn *insn)
case REG:
new_rtx = instantiate_new_reg (x, &offset);
- if (new_rtx == NULL)
+ if (new_rtx == NULL_RTX)
continue;
if (known_eq (offset, 0))
x = new_rtx;
@@ -1725,7 +1725,7 @@ instantiate_virtual_regs_in_insn (rtx_insn *insn)
case SUBREG:
new_rtx = instantiate_new_reg (SUBREG_REG (x), &offset);
- if (new_rtx == NULL)
+ if (new_rtx == NULL_RTX)
continue;
if (maybe_ne (offset, 0))
{
@@ -2562,7 +2562,7 @@ assign_parm_find_entry_rtl (struct assign_parm_data_all *all,
named_arg.named = true;
tem = targetm.calls.function_incoming_arg (all->args_so_far,
named_arg);
- in_regs = tem != NULL;
+ in_regs = tem != NULL_RTX;
}
}
@@ -2776,7 +2776,7 @@ assign_parm_adjust_entry_rtl (struct assign_parm_data_one *data)
/* If we didn't decide this parm came in a register, by default it came
on the stack. */
- else if (entry_parm == NULL)
+ else if (entry_parm == NULL_RTX)
entry_parm = stack_parm;
/* When an argument is passed in multiple locations, we can't make use
@@ -2846,14 +2846,14 @@ assign_parm_adjust_stack_rtl (struct assign_parm_data_one *data)
|| (data->nominal_type
&& TYPE_ALIGN (data->nominal_type) > MEM_ALIGN (stack_parm)
&& MEM_ALIGN (stack_parm) < PREFERRED_STACK_BOUNDARY)))
- stack_parm = NULL;
+ stack_parm = NULL_RTX;
/* If parm was passed in memory, and we need to convert it on entry,
don't store it back in that same slot. */
else if (data->entry_parm == stack_parm
&& data->nominal_mode != BLKmode
&& data->nominal_mode != data->passed_mode)
- stack_parm = NULL;
+ stack_parm = NULL_RTX;
/* If stack protection is in effect for this function, don't leave any
pointers in their passed stack slots. */
@@ -2861,7 +2861,7 @@ assign_parm_adjust_stack_rtl (struct assign_parm_data_one *data)
&& (flag_stack_protect == SPCT_FLAG_ALL
|| data->arg.pass_by_reference
|| POINTER_TYPE_P (data->nominal_type)))
- stack_parm = NULL;
+ stack_parm = NULL_RTX;
data->stack_parm = stack_parm;
}
diff --git a/gcc/genattrtab.cc b/gcc/genattrtab.cc
index a5f7c0b8764..60e6f2520ae 100644
--- a/gcc/genattrtab.cc
+++ b/gcc/genattrtab.cc
@@ -1379,14 +1379,14 @@ fill_attr (class attr_desc *attr)
{
/* If no value is specified for this insn for this attribute, use the
default. */
- value = NULL;
+ value = NULL_RTX;
if (XVEC (id->def, id->vec_idx))
for (i = 0; i < XVECLEN (id->def, id->vec_idx); i++)
if (! strcmp_check (XSTR (XEXP (XVECEXP (id->def, id->vec_idx, i), 0), 0),
attr->name))
value = XEXP (XVECEXP (id->def, id->vec_idx, i), 1);
- if (value == NULL)
+ if (value == NULL_RTX)
av = attr->default_val;
else
av = get_attr_value (id->loc, value, attr, id->insn_code);
@@ -3290,7 +3290,7 @@ find_attrs_to_cache (rtx exp, bool create)
const char *name;
class attr_desc *attr;
- if (exp == NULL)
+ if (exp == NULL_RTX)
return;
switch (GET_CODE (exp))
@@ -3976,7 +3976,7 @@ walk_attr_value (rtx exp)
const char *fmt;
RTX_CODE code;
- if (exp == NULL)
+ if (exp == NULL_RTX)
return;
code = GET_CODE (exp);
diff --git a/gcc/genrecog.cc b/gcc/genrecog.cc
index 04a5533ca4b..2a6d0a4a935 100644
--- a/gcc/genrecog.cc
+++ b/gcc/genrecog.cc
@@ -396,7 +396,7 @@ find_operand (rtx pattern, int n, rtx stop)
}
}
- return NULL;
+ return NULL_RTX;
}
/* Search for and return operand M, such that it has a matching
@@ -447,7 +447,7 @@ find_matching_operand (rtx pattern, int n)
}
}
- return NULL;
+ return NULL_RTX;
}
/* In DEFINE_EXPAND, DEFINE_SPLIT, and DEFINE_PEEPHOLE2, we
diff --git a/gcc/gensupport.cc b/gcc/gensupport.cc
index f9efc6eb757..0cb70c4c733 100644
--- a/gcc/gensupport.cc
+++ b/gcc/gensupport.cc
@@ -1205,7 +1205,7 @@ alter_predicate_for_insn (rtx pattern, int alt, int max_op,
{
error_at (loc, "too many alternatives for operand %d",
XINT (pattern, 0));
- return NULL;
+ return NULL_RTX;
}
/* Replicate C as needed to fill out ALT alternatives. */
@@ -1248,7 +1248,7 @@ alter_predicate_for_insn (rtx pattern, int alt, int max_op,
{
case 'e': case 'u':
r = alter_predicate_for_insn (XEXP (pattern, i), alt, max_op, loc);
- if (r == NULL)
+ if (r == NULL_RTX)
return r;
break;
@@ -1257,7 +1257,7 @@ alter_predicate_for_insn (rtx pattern, int alt, int max_op,
{
r = alter_predicate_for_insn (XVECEXP (pattern, i, j),
alt, max_op, loc);
- if (r == NULL)
+ if (r == NULL_RTX)
return r;
}
break;
@@ -1310,7 +1310,7 @@ alter_constraints (rtx pattern, int n_dup, constraints_handler_t alter)
{
case 'e': case 'u':
r = alter_constraints (XEXP (pattern, i), n_dup, alter);
- if (r == NULL)
+ if (r == NULL_RTX)
return r;
break;
@@ -1318,7 +1318,7 @@ alter_constraints (rtx pattern, int n_dup, constraints_handler_t alter)
for (j = XVECLEN (pattern, i) - 1; j >= 0; --j)
{
r = alter_constraints (XVECEXP (pattern, i, j), n_dup, alter);
- if (r == NULL)
+ if (r == NULL_RTX)
return r;
}
break;
@@ -2137,7 +2137,7 @@ replace_duplicating_operands_in_pattern (rtx pattern)
if (match_operand_entries_in_pattern[opno] == NULL)
{
match_operand_entries_in_pattern[opno] = pattern;
- return NULL;
+ return NULL_RTX;
}
else
{
@@ -2147,7 +2147,7 @@ replace_duplicating_operands_in_pattern (rtx pattern)
{
error ("duplicated match_operands with different predicates were"
" found.");
- return NULL;
+ return NULL_RTX;
}
return generate_match_dup (opno);
}
@@ -2175,7 +2175,7 @@ replace_duplicating_operands_in_pattern (rtx pattern)
break;
}
}
- return NULL;
+ return NULL_RTX;
}
/* The routine modifies given input PATTERN of define_subst, replacing
@@ -2476,7 +2476,7 @@ static void
gen_mnemonic_attr (void)
{
class queue_elem *elem;
- rtx mnemonic_attr = NULL;
+ rtx mnemonic_attr = NULL_RTX;
htab_t mnemonic_htab;
const char *str, *p;
int i;
diff --git a/gcc/hooks.cc b/gcc/hooks.cc
index e83add43289..58de9aaa0b7 100644
--- a/gcc/hooks.cc
+++ b/gcc/hooks.cc
@@ -391,14 +391,14 @@ hook_rtx_rtx_identity (rtx x)
rtx
hook_rtx_rtx_null (rtx)
{
- return NULL;
+ return NULL_RTX;
}
/* Generic hook that takes a tree and an int and returns NULL_RTX. */
rtx
hook_rtx_tree_int_null (tree, int)
{
- return NULL;
+ return NULL_RTX;
}
/* Generic hook that takes a machine mode and returns an unsigned int 0. */
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 868eda93251..53ba5b70e8e 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -2505,7 +2505,7 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
cond = canonicalize_condition (if_info->jump, cond, reverse,
earliest, target, have_cbranchcc4, true);
if (! cond || ! reg_mentioned_p (target, cond))
- return NULL;
+ return NULL_RTX;
/* We almost certainly searched back to a different place.
Need to re-verify correct lifetimes. */
@@ -2513,14 +2513,14 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
/* X may not be mentioned in the range (cond_earliest, jump]. */
for (insn = if_info->jump; insn != *earliest; insn = PREV_INSN (insn))
if (INSN_P (insn) && reg_overlap_mentioned_p (if_info->x, PATTERN (insn)))
- return NULL;
+ return NULL_RTX;
/* A and B may not be modified in the range [cond_earliest, jump). */
for (insn = *earliest; insn != if_info->jump; insn = NEXT_INSN (insn))
if (INSN_P (insn)
&& (modified_in_p (if_info->a, insn)
|| modified_in_p (if_info->b, insn)))
- return NULL;
+ return NULL_RTX;
return cond;
}
diff --git a/gcc/ira-build.cc b/gcc/ira-build.cc
index 93e46033170..d3cb15c059f 100644
--- a/gcc/ira-build.cc
+++ b/gcc/ira-build.cc
@@ -1851,7 +1851,7 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p)
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
- if (outer != NULL && GET_CODE (outer) == SUBREG)
+ if (outer != NULL_RTX && GET_CODE (outer) == SUBREG)
{
machine_mode wmode = GET_MODE (outer);
if (partial_subreg_p (ALLOCNO_WMODE (a), wmode))
diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
index 1fb2958bddd..888eb27386d 100644
--- a/gcc/ira-color.cc
+++ b/gcc/ira-color.cc
@@ -2255,7 +2255,7 @@ allocnos_conflict_by_live_ranges_p (ira_allocno_t a1, ira_allocno_t a2)
return false;
reg1 = regno_reg_rtx[ALLOCNO_REGNO (a1)];
reg2 = regno_reg_rtx[ALLOCNO_REGNO (a2)];
- if (reg1 != NULL && reg2 != NULL
+ if (reg1 != NULL_RTX && reg2 != NULL_RTX
&& ORIGINAL_REGNO (reg1) == ORIGINAL_REGNO (reg2))
return false;
diff --git a/gcc/ira-lives.cc b/gcc/ira-lives.cc
index 6a3901ee234..7c8174f2f78 100644
--- a/gcc/ira-lives.cc
+++ b/gcc/ira-lives.cc
@@ -1074,7 +1074,7 @@ find_call_crossed_cheap_reg (rtx_insn *insn)
rtx cheap_reg = NULL_RTX;
rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
- while (exp != NULL)
+ while (exp != NULL_RTX)
{
rtx x = XEXP (exp, 0);
if (GET_CODE (x) == SET)
@@ -1084,7 +1084,7 @@ find_call_crossed_cheap_reg (rtx_insn *insn)
}
exp = XEXP (exp, 1);
}
- if (exp != NULL)
+ if (exp != NULL_RTX)
{
basic_block bb = BLOCK_FOR_INSN (insn);
rtx reg = SET_SRC (exp);
diff --git a/gcc/ira.cc b/gcc/ira.cc
index 02dea5d49ee..f94345b472f 100644
--- a/gcc/ira.cc
+++ b/gcc/ira.cc
@@ -1858,7 +1858,7 @@ ira_setup_alts (rtx_insn *insn)
default:
{
enum constraint_num cn = lookup_constraint (p);
- rtx mem = NULL;
+ rtx mem = NULL_RTX;
switch (get_constraint_type (cn))
{
case CT_REGISTER:
@@ -5034,7 +5034,7 @@ interesting_dest_for_shprep_1 (rtx set, basic_block call_dom)
if (!REG_P (src) || !HARD_REGISTER_P (src)
|| !REG_P (dest) || HARD_REGISTER_P (dest)
|| (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest))))
- return NULL;
+ return NULL_RTX;
return dest;
}
@@ -5048,14 +5048,14 @@ static rtx
interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom)
{
if (!INSN_P (insn))
- return NULL;
+ return NULL_RTX;
rtx pat = PATTERN (insn);
if (GET_CODE (pat) == SET)
return interesting_dest_for_shprep_1 (pat, call_dom);
if (GET_CODE (pat) != PARALLEL)
- return NULL;
- rtx ret = NULL;
+ return NULL_RTX;
+ rtx ret = NULL_RTX;
for (int i = 0; i < XVECLEN (pat, 0); i++)
{
rtx sub = XVECEXP (pat, 0, i);
@@ -5063,10 +5063,10 @@ interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom)
continue;
if (GET_CODE (sub) != SET
|| side_effects_p (sub))
- return NULL;
+ return NULL_RTX;
rtx dest = interesting_dest_for_shprep_1 (sub, call_dom);
if (dest && ret)
- return NULL;
+ return NULL_RTX;
if (dest)
ret = dest;
}
diff --git a/gcc/jump.cc b/gcc/jump.cc
index 7a5db118e7a..f2e125ed25e 100644
--- a/gcc/jump.cc
+++ b/gcc/jump.cc
@@ -246,7 +246,7 @@ maybe_propagate_label_ref (rtx_insn *jump_insn, rtx_insn *prev_nonjump_insn)
rtx label_note, pc, pc_src;
pc = pc_set (jump_insn);
- pc_src = pc != NULL ? SET_SRC (pc) : NULL;
+ pc_src = pc != NULL_RTX ? SET_SRC (pc) : NULL;
label_note = find_reg_note (prev_nonjump_insn, REG_LABEL_OPERAND, NULL);
/* If the previous non-jump insn sets something to a label,
@@ -258,12 +258,12 @@ maybe_propagate_label_ref (rtx_insn *jump_insn, rtx_insn *prev_nonjump_insn)
may refer to the item being set only directly or as one of the
arms in an IF_THEN_ELSE. */
- if (label_note != NULL && pc_src != NULL)
+ if (label_note != NULL_RTX && pc_src != NULL_RTX)
{
rtx label_set = single_set (prev_nonjump_insn);
- rtx label_dest = label_set != NULL ? SET_DEST (label_set) : NULL;
+ rtx label_dest = label_set != NULL_RTX ? SET_DEST (label_set) : NULL;
- if (label_set != NULL
+ if (label_set != NULL_RTX
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
&& GET_CODE (SET_SRC (label_set)) == LABEL_REF
@@ -993,7 +993,7 @@ onlyjump_p (const rtx_insn *insn)
return 0;
set = single_set (insn);
- if (set == NULL)
+ if (set == NULL_RTX)
return 0;
if (GET_CODE (SET_DEST (set)) != PC)
return 0;
@@ -1452,7 +1452,7 @@ redirect_jump_1 (rtx_insn *jump, rtx nlabel)
asmop = extract_asm_operands (PATTERN (jump));
if (asmop)
{
- if (nlabel == NULL)
+ if (nlabel == NULL_RTX)
return 0;
gcc_assert (ASM_OPERANDS_LABEL_LENGTH (asmop) == 1);
loc = &ASM_OPERANDS_LABEL (asmop, 0);
@@ -1605,7 +1605,7 @@ invert_jump_1 (rtx_jump_insn *jump, rtx nlabel)
int ok;
ochanges = num_validated_changes ();
- if (x == NULL)
+ if (x == NULL_RTX)
return 0;
ok = invert_exp_1 (SET_SRC (x), jump);
gcc_assert (ok);
diff --git a/gcc/lra-coalesce.cc b/gcc/lra-coalesce.cc
index 04a5bbd714b..ec866337009 100644
--- a/gcc/lra-coalesce.cc
+++ b/gcc/lra-coalesce.cc
@@ -267,7 +267,7 @@ lra_coalesce (void)
{
mv = sorted_moves[i];
set = single_set (mv);
- lra_assert (set != NULL && REG_P (SET_SRC (set))
+ lra_assert (set != NULL_RTX && REG_P (SET_SRC (set))
&& REG_P (SET_DEST (set)));
sregno = REGNO (SET_SRC (set));
dregno = REGNO (SET_DEST (set));
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 4dc2d70c402..46aa7910f61 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -276,7 +276,7 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class,
where other reload pseudos are no longer allocatable. */
|| (!allow_all_reload_class_changes_p
&& INSN_UID (curr_insn) >= new_insn_uid_start
- && src != NULL
+ && src != NULL_RTX
&& ((REG_P (src) || MEM_P (src))
|| (GET_CODE (src) == SUBREG
&& (REG_P (SUBREG_REG (src)) || MEM_P (SUBREG_REG (src)))))))
@@ -5009,7 +5009,7 @@ insn_rhs_dead_pseudo_p (rtx_insn *insn)
{
rtx set = single_set (insn);
- gcc_assert (set != NULL);
+ gcc_assert (set != NULL_RTX);
return dead_pseudo_p (SET_SRC (set), insn);
}
@@ -5816,7 +5816,7 @@ inherit_reload_reg (bool def_p, int original_regno,
{
usage_insn = next_usage_insns;
lra_assert (NONDEBUG_INSN_P (usage_insn));
- next_usage_insns = NULL;
+ next_usage_insns = NULL_RTX;
}
else
{
@@ -6148,7 +6148,7 @@ split_reg (bool before_p, int original_regno, rtx_insn *insn,
bitmap_set_bit (&lra_split_regs, new_regno);
if (to != NULL)
{
- lra_assert (next_usage_insns == NULL);
+ lra_assert (next_usage_insns == NULL_RTX);
usage_insn = to;
after_p = TRUE;
}
@@ -6380,7 +6380,7 @@ process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
{
/* We have a subsequent insn using the invariant. */
insn_set = single_set (insn);
- lra_assert (insn_set != NULL);
+ lra_assert (insn_set != NULL_RTX);
insn_reg = SET_DEST (insn_set);
lra_assert (REG_P (insn_reg));
insn_regno = REGNO (insn_reg);
diff --git a/gcc/lra-remat.cc b/gcc/lra-remat.cc
index 681dcf36331..31a7380c1b1 100644
--- a/gcc/lra-remat.cc
+++ b/gcc/lra-remat.cc
@@ -448,7 +448,7 @@ create_cands (void)
int nop;
/* See if this is an output reload for a previous insn. */
- if (set != NULL
+ if (set != NULL_RTX
&& REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)))
{
rtx dstreg = SET_DEST (set);
diff --git a/gcc/optabs-libfuncs.cc b/gcc/optabs-libfuncs.cc
index f1abe6916d3..476613085ee 100644
--- a/gcc/optabs-libfuncs.cc
+++ b/gcc/optabs-libfuncs.cc
@@ -89,12 +89,12 @@ convert_optab_libfunc (convert_optab optab, machine_mode mode1,
= &convlib_def[optab - FIRST_CONV_OPTAB];
if (d->libcall_gen == NULL)
- return NULL;
+ return NULL_RTX;
d->libcall_gen (optab, d->libcall_basename, mode1, mode2);
slot = libfunc_hash->find_slot (&e, NO_INSERT);
if (!slot)
- return NULL;
+ return NULL_RTX;
}
return (*slot)->libfunc;
}
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index a12333c7169..ea0d583489b 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -447,7 +447,7 @@ expand_vector_broadcast (machine_mode vmode, rtx op)
}
if (!GET_MODE_NUNITS (vmode).is_constant (&n))
- return NULL;
+ return NULL_RTX;
/* ??? If the target doesn't have a vec_init, then we have no easy way
of performing this operation. Most of this sort of generic support
@@ -455,7 +455,7 @@ expand_vector_broadcast (machine_mode vmode, rtx op)
icode = convert_optab_handler (vec_init_optab, vmode,
GET_MODE_INNER (vmode));
if (icode == CODE_FOR_nothing)
- return NULL;
+ return NULL_RTX;
vec = rtvec_alloc (n);
for (int i = 0; i < n; ++i)
@@ -3060,11 +3060,11 @@ lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
{
rtx ret;
ret = lowpart_subreg (omode, val, imode);
- if (ret == NULL)
+ if (ret == NULL_RTX)
{
val = force_reg (imode, val);
ret = lowpart_subreg (omode, val, imode);
- gcc_assert (ret != NULL);
+ gcc_assert (ret != NULL_RTX);
}
return ret;
}
@@ -6520,7 +6520,7 @@ expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target)
sel = expand_simple_binop (selmode, ASHIFT, sel,
gen_int_shift_amount (selmode, exact_log2 (u)),
NULL, 0, OPTAB_DIRECT);
- gcc_assert (sel != NULL);
+ gcc_assert (sel != NULL_RTX);
/* Broadcast the low byte each element into each of its bytes.
The encoding has U interleaved stepped patterns, one for each
@@ -6532,7 +6532,7 @@ expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target)
const_sel.quick_push (i * u + low_byte_in_u);
sel = gen_lowpart (qimode, sel);
sel = expand_vec_perm_const (qimode, sel, sel, const_sel, qimode, NULL);
- gcc_assert (sel != NULL);
+ gcc_assert (sel != NULL_RTX);
/* Add the byte offset to each byte element. */
/* Note that the definition of the indicies here is memory ordering,
@@ -6543,7 +6543,7 @@ expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target)
tmp = byte_indices.build ();
sel_qi = expand_simple_binop (qimode, PLUS, sel, tmp,
sel, 0, OPTAB_DIRECT);
- gcc_assert (sel_qi != NULL);
+ gcc_assert (sel_qi != NULL_RTX);
tmp = mode != qimode ? gen_reg_rtx (qimode) : target;
tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0),
@@ -6825,7 +6825,7 @@ maybe_emit_sync_lock_test_and_set (rtx target, rtx mem, rtx val,
if (!can_compare_and_swap_p (mode, false))
{
rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, mode);
- if (libfunc != NULL)
+ if (libfunc != NULL_RTX)
{
rtx addr;
@@ -7135,7 +7135,7 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval,
/* Also check for library support for __sync_val_compare_and_swap. */
libfunc = optab_libfunc (sync_compare_and_swap_optab, mode);
- if (libfunc != NULL)
+ if (libfunc != NULL_RTX)
{
rtx addr = convert_memory_address (ptr_mode, XEXP (mem, 0));
rtx target = emit_library_call_value (libfunc, NULL_RTX, LCT_NORMAL,
@@ -7756,7 +7756,7 @@ expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
get_atomic_op_for_code (&optab, code);
libfunc = optab_libfunc (after ? optab.fetch_after
: optab.fetch_before, mode);
- if (libfunc == NULL
+ if (libfunc == NULL_RTX
&& (after || unused_result || optab.reverse_code != UNKNOWN))
{
fixup = true;
@@ -7765,7 +7765,7 @@ expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
libfunc = optab_libfunc (after ? optab.fetch_before
: optab.fetch_after, mode);
}
- if (libfunc != NULL)
+ if (libfunc != NULL_RTX)
{
rtx addr = convert_memory_address (ptr_mode, XEXP (mem, 0));
result = emit_library_call_value (libfunc, NULL, LCT_NORMAL, mode,
@@ -7818,7 +7818,7 @@ expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
insn = get_insns ();
end_sequence ();
- if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn))
+ if (t1 != NULL_RTX && expand_compare_and_swap_loop (mem, t0, t1, insn))
return target;
}
diff --git a/gcc/read-rtl-function.cc b/gcc/read-rtl-function.cc
index b89a811e037..723025c4a92 100644
--- a/gcc/read-rtl-function.cc
+++ b/gcc/read-rtl-function.cc
@@ -1424,7 +1424,7 @@ lookup_global_register (int regno)
return return_address_pointer_rtx;
#endif
- return NULL;
+ return NULL_RTX;
}
/* Ensure that the backend can cope with a REG with regno REGNO.
diff --git a/gcc/read-rtl.cc b/gcc/read-rtl.cc
index 8cb25aebdbb..e24035247da 100644
--- a/gcc/read-rtl.cc
+++ b/gcc/read-rtl.cc
@@ -2035,7 +2035,7 @@ rtx_reader::read_nested_rtx ()
read_name (&name);
if (strcmp (name.string, "nil") == 0)
- return_rtx = NULL;
+ return_rtx = NULL_RTX;
else
return_rtx = read_rtx_code (name.string);
diff --git a/gcc/recog.cc b/gcc/recog.cc
index fd09145d45e..75190e35e27 100644
--- a/gcc/recog.cc
+++ b/gcc/recog.cc
@@ -528,7 +528,7 @@ void
confirm_change_group (void)
{
int i;
- rtx last_object = NULL;
+ rtx last_object = NULL_RTX;
gcc_assert (temporarily_undone_changes == 0);
for (i = 0; i < num_changes; i++)
@@ -987,8 +987,8 @@ bool
validate_simplify_insn (rtx_insn *insn)
{
int i;
- rtx pat = NULL;
- rtx newpat = NULL;
+ rtx pat = NULL_RTX;
+ rtx newpat = NULL_RTX;
pat = PATTERN (insn);
@@ -1940,7 +1940,7 @@ extract_asm_operands (rtx body)
default:
break;
}
- return NULL;
+ return NULL_RTX;
}
/* If BODY is an insn body that uses ASM_OPERANDS,
@@ -1955,7 +1955,7 @@ asm_noperands (const_rtx body)
rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
int i, n_sets = 0;
- if (asm_op == NULL)
+ if (asm_op == NULL_RTX)
{
if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2
&& GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
@@ -2271,7 +2271,7 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
/* FALLTHRU */
default:
cn = lookup_constraint (constraint);
- rtx mem = NULL;
+ rtx mem = NULL_RTX;
switch (get_constraint_type (cn))
{
case CT_REGISTER:
@@ -3838,7 +3838,7 @@ copy_frame_info_to_split_insn (rtx_insn *old_insn, rtx_insn *new_insn)
/* The old insn had better have been simple, or annotated. */
old_set = single_set (old_insn);
- gcc_assert (old_set != NULL);
+ gcc_assert (old_set != NULL_RTX);
new_set = single_set (new_insn);
if (!new_set || !rtx_equal_p (new_set, old_set))
diff --git a/gcc/regcprop.cc b/gcc/regcprop.cc
index f426f4fedcd..1d9f44d8b0a 100644
--- a/gcc/regcprop.cc
+++ b/gcc/regcprop.cc
@@ -877,7 +877,7 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd)
special case below. */
if (set
&& reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set)))
- set = NULL;
+ set = NULL_RTX;
}
/* We need to keep CFI info correct, and the same on all paths,
diff --git a/gcc/reload.cc b/gcc/reload.cc
index d079bc120d5..46a707d44a6 100644
--- a/gcc/reload.cc
+++ b/gcc/reload.cc
@@ -4638,7 +4638,7 @@ alternative_allows_const_pool_ref (rtx mem ATTRIBUTE_UNUSED,
{
enum constraint_num cn = lookup_constraint (constraint);
if (insn_extra_memory_constraint (cn)
- && (mem == NULL || constraint_satisfied_p (mem, cn)))
+ && (mem == NULL_RTX || constraint_satisfied_p (mem, cn)))
return true;
}
return false;
@@ -6166,14 +6166,14 @@ find_reloads_subreg_address (rtx x, int opnum, enum reload_type type,
paradoxical subregs where no address reload was required. */
if (paradoxical_subreg_p (x))
- return NULL;
+ return NULL_RTX;
if (WORD_REGISTER_OPERATIONS
&& partial_subreg_p (outer_mode, inner_mode)
&& known_equal_after_align_down (GET_MODE_SIZE (outer_mode) - 1,
GET_MODE_SIZE (inner_mode) - 1,
UNITS_PER_WORD))
- return NULL;
+ return NULL_RTX;
/* Since we don't attempt to handle paradoxical subregs, we can just
call into simplify_subreg, which will handle all remaining checks
@@ -6182,7 +6182,7 @@ find_reloads_subreg_address (rtx x, int opnum, enum reload_type type,
offset = SUBREG_BYTE (x);
tem = simplify_subreg (outer_mode, orig, inner_mode, offset);
if (!tem || !MEM_P (tem))
- return NULL;
+ return NULL_RTX;
/* Now push all required address reloads, if any. */
reloaded = find_reloads_address (GET_MODE (tem), &tem,
diff --git a/gcc/reload1.cc b/gcc/reload1.cc
index 9ec2cb9baf4..8c8fbcb7461 100644
--- a/gcc/reload1.cc
+++ b/gcc/reload1.cc
@@ -4416,7 +4416,7 @@ static void
fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
{
rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
- if (note == NULL)
+ if (note == NULL_RTX)
return;
if (!insn_could_throw_p (insn))
remove_note (insn, note);
diff --git a/gcc/rtl-error.cc b/gcc/rtl-error.cc
index eabdb3388bf..4d63e0d561a 100644
--- a/gcc/rtl-error.cc
+++ b/gcc/rtl-error.cc
@@ -50,7 +50,7 @@ location_for_asm (const rtx_insn *insn)
&& GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
asmop = XVECEXP (body, 0, 0);
else
- asmop = NULL;
+ asmop = NULL_RTX;
if (asmop)
loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc
index b7948ecfad1..8214e4032fe 100644
--- a/gcc/rtlanal.cc
+++ b/gcc/rtlanal.cc
@@ -1546,7 +1546,7 @@ record_hard_reg_uses (rtx *px, void *data)
rtx
single_set_2 (const rtx_insn *insn, const_rtx pat)
{
- rtx set = NULL;
+ rtx set = NULL_RTX;
int set_verified = 1;
int i;
@@ -1574,7 +1574,7 @@ single_set_2 (const rtx_insn *insn, const_rtx pat)
{
if (find_reg_note (insn, REG_UNUSED, SET_DEST (set))
&& !side_effects_p (set))
- set = NULL;
+ set = NULL_RTX;
else
set_verified = 1;
}
@@ -2584,7 +2584,7 @@ find_reg_equal_equiv_note (const_rtx insn)
return 0;
return link;
}
- return NULL;
+ return NULL_RTX;
}
/* Check whether INSN is a single_set whose source is known to be
diff --git a/gcc/rtlhooks.cc b/gcc/rtlhooks.cc
index 989d3c98807..acd8e34f9f7 100644
--- a/gcc/rtlhooks.cc
+++ b/gcc/rtlhooks.cc
@@ -79,7 +79,7 @@ rtx
reg_num_sign_bit_copies_general (const_rtx, scalar_int_mode, scalar_int_mode,
unsigned int *)
{
- return NULL;
+ return NULL_RTX;
}
rtx
diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc
index 2aa6623ad2e..356e1a3d0c5 100644
--- a/gcc/sched-deps.cc
+++ b/gcc/sched-deps.cc
@@ -1167,7 +1167,7 @@ update_dep (dep_t dep, dep_t new_dep,
else
{
/* Both are speculative. Merge probabilities. */
- if (mem1 != NULL)
+ if (mem1 != NULL_RTX)
{
dw_t dw;
@@ -1217,7 +1217,7 @@ add_or_update_dep_1 (dep_t new_dep, bool resolved_p,
&& DEP_PRO (new_dep) != DEP_CON (new_dep));
if (flag_checking)
- check_dep (new_dep, mem1 != NULL);
+ check_dep (new_dep, mem1 != NULL_RTX);
if (true_dependency_cache != NULL)
{
diff --git a/gcc/sel-sched-ir.cc b/gcc/sel-sched-ir.cc
index 9241987d4fd..d22ff4c3c70 100644
--- a/gcc/sel-sched-ir.cc
+++ b/gcc/sel-sched-ir.cc
@@ -1129,7 +1129,7 @@ hash_with_unspec_callback (const_rtx x, machine_mode mode ATTRIBUTE_UNUSED,
static bool
lhs_and_rhs_separable_p (rtx lhs, rtx rhs)
{
- if (lhs == NULL || rhs == NULL)
+ if (lhs == NULL_RTX || rhs == NULL_RTX)
return false;
/* Do not schedule constants as rhs: no point to use reg, if const
@@ -2548,7 +2548,7 @@ deps_init_id_finish_insn (void)
rtx lhs = IDATA_LHS (deps_init_id_data.id);
rtx rhs = IDATA_RHS (deps_init_id_data.id);
- if (lhs == NULL || rhs == NULL || !lhs_and_rhs_separable_p (lhs, rhs)
+ if (lhs == NULL_RTX || rhs == NULL_RTX || !lhs_and_rhs_separable_p (lhs, rhs)
|| deps_init_id_data.force_use_p)
{
/* This should be a USE, as we don't want to schedule its RHS
@@ -3579,7 +3579,7 @@ lhs_of_insn_equals_to_dest_p (insn_t insn, rtx dest)
{
rtx lhs = INSN_LHS (insn);
- if (lhs == NULL || dest == NULL)
+ if (lhs == NULL_RTX || dest == NULL_RTX)
return false;
return rtx_equal_p (lhs, dest);
diff --git a/gcc/sel-sched.cc b/gcc/sel-sched.cc
index cb1cf75bfe4..481f4734ec5 100644
--- a/gcc/sel-sched.cc
+++ b/gcc/sel-sched.cc
@@ -1784,7 +1784,7 @@ create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
check_ds);
- gcc_assert (check_pattern != NULL);
+ gcc_assert (check_pattern != NULL_RTX);
/* Emit check. */
insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
diff --git a/gcc/shrink-wrap.cc b/gcc/shrink-wrap.cc
index b8d7b557130..f4c4945d0b8 100644
--- a/gcc/shrink-wrap.cc
+++ b/gcc/shrink-wrap.cc
@@ -235,7 +235,7 @@ move_insn_for_shrink_wrap (basic_block bb, rtx_insn *insn,
case REG:
/* Fail if we see a second inner register. */
- if (src_inner != NULL)
+ if (src_inner != NULL_RTX)
return false;
src_inner = x;
break;
@@ -250,7 +250,7 @@ move_insn_for_shrink_wrap (basic_block bb, rtx_insn *insn,
}
}
- if (src_inner != NULL)
+ if (src_inner != NULL_RTX)
src = src_inner;
}
diff --git a/gcc/valtrack.cc b/gcc/valtrack.cc
index 22f4ddcb3e9..24912e37032 100644
--- a/gcc/valtrack.cc
+++ b/gcc/valtrack.cc
@@ -626,7 +626,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
/* We may have dangling bits in debug->used for registers that were part
of a multi-register use, one component of which has been reset. */
- if (reg == NULL)
+ if (reg == NULL_RTX)
{
gcc_checking_assert (!uses);
if (!global)
@@ -669,7 +669,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
/* ??? Should we try to extract it from a PARALLEL? */
if (!set)
- breg = NULL;
+ breg = NULL_RTX;
/* Cool, it's the same REG, we can use SRC. */
else if (dest == reg)
breg = cleanup_auto_inc_dec (src, VOIDmode);
@@ -677,14 +677,14 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
{
/* Hmm... Something's fishy, we should be setting REG here. */
if (REGNO (dest) != REGNO (reg))
- breg = NULL;
+ breg = NULL_RTX;
/* If we're not overwriting all the hardware registers that
setting REG in its mode would, we won't know what to bind
the debug temp to. ??? We could bind the debug_expr to a
CONCAT or PARALLEL with the split multi-registers, and
replace them as we found the corresponding sets. */
else if (REG_NREGS (reg) != REG_NREGS (dest))
- breg = NULL;
+ breg = NULL_RTX;
/* Ok, it's the same (hardware) REG, but with a different
mode, so SUBREG it. */
else
@@ -696,18 +696,18 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
{
/* We should be setting REG here. Lose. */
if (REGNO (SUBREG_REG (dest)) != REGNO (reg))
- breg = NULL;
+ breg = NULL_RTX;
/* Lose if we're setting something other than the lowpart of
REG. */
else if (!subreg_lowpart_p (dest))
- breg = NULL;
+ breg = NULL_RTX;
/* If we're not overwriting all the hardware registers that
setting REG in its mode would, we won't know what to bind
the debug temp to. */
else if (REGNO (reg) < FIRST_PSEUDO_REGISTER
&& (REG_NREGS (reg)
!= hard_regno_nregs (REGNO (reg), GET_MODE (dest))))
- breg = NULL;
+ breg = NULL_RTX;
/* Yay, we can use SRC, just adjust its mode. */
else
breg = debug_lowpart_subreg (GET_MODE (reg),
@@ -716,7 +716,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
}
/* Oh well, we're out of luck. */
else
- breg = NULL;
+ breg = NULL_RTX;
/* We couldn't figure out the value stored in REG, so reset all
of its pending debug uses. */
diff --git a/gcc/var-tracking.cc b/gcc/var-tracking.cc
index d8dafa5481a..991cf2152fe 100644
--- a/gcc/var-tracking.cc
+++ b/gcc/var-tracking.cc
@@ -2575,7 +2575,7 @@ val_reset (dataflow_set *set, decl_or_value dv)
}
}
- cval = NULL;
+ cval = NULL_RTX;
for (node = var->var_part[0].loc_chain; node; node = node->next)
if (GET_CODE (node->loc) == VALUE
&& canon_value_cmp (node->loc, cval))
@@ -3987,7 +3987,7 @@ variable_merge_over_cur (variable *s1var, struct dfset_merge *dsm)
if (dv_is_value_p (dv))
val = dv_as_value (dv);
else
- val = NULL;
+ val = NULL_RTX;
s2var = shared_hash_find_1 (dsm->src->vars, dv, dvhash);
if (!s2var)
@@ -5386,7 +5386,7 @@ var_lowpart (machine_mode mode, rtx loc)
return loc;
if (!REG_P (loc) && !MEM_P (loc))
- return NULL;
+ return NULL_RTX;
poly_uint64 offset = byte_lowpart_offset (mode, GET_MODE (loc));
@@ -5459,7 +5459,7 @@ static rtx
replace_expr_with_values (rtx loc)
{
if (REG_P (loc) || GET_CODE (loc) == ENTRY_VALUE)
- return NULL;
+ return NULL_RTX;
else if (MEM_P (loc))
{
cselib_val *addr = cselib_lookup (XEXP (loc, 0),
@@ -5468,7 +5468,7 @@ replace_expr_with_values (rtx loc)
if (addr)
return replace_equiv_address_nv (loc, addr->val_rtx);
else
- return NULL;
+ return NULL_RTX;
}
else
return cselib_subst_to_values (loc, VOIDmode);
@@ -5705,7 +5705,7 @@ add_uses (rtx loc, struct count_use_info *cui)
{
machine_mode mode2;
enum micro_operation_type type2;
- rtx nloc = NULL;
+ rtx nloc = NULL_RTX;
bool resolvable = REG_P (vloc) || MEM_P (vloc);
if (resolvable)
@@ -5948,7 +5948,7 @@ add_stores (rtx loc, const_rtx expr, void *cuip)
struct count_use_info *cui = (struct count_use_info *)cuip;
basic_block bb = cui->bb;
micro_operation mo;
- rtx oloc = loc, nloc, src = NULL;
+ rtx oloc = loc, nloc, src = NULL_RTX;
enum micro_operation_type type = use_type (loc, cui, &mode);
bool track_p = false;
cselib_val *v;
@@ -5987,7 +5987,7 @@ add_stores (rtx loc, const_rtx expr, void *cuip)
src = var_lowpart (mode2, SET_SRC (expr));
loc = var_lowpart (mode2, loc);
- if (src == NULL)
+ if (src == NULL_RTX)
{
mo.type = MO_SET;
mo.u.loc = loc;
@@ -6052,7 +6052,7 @@ add_stores (rtx loc, const_rtx expr, void *cuip)
src = var_lowpart (mode2, SET_SRC (expr));
loc = var_lowpart (mode2, loc);
- if (src == NULL)
+ if (src == NULL_RTX)
{
mo.type = MO_SET;
mo.u.loc = loc;
@@ -7782,7 +7782,7 @@ set_slot_part (dataflow_set *set, rtx loc, variable **slot,
to do. */
if (node->init < initialized)
node->init = initialized;
- if (set_src != NULL)
+ if (set_src != NULL_RTX)
node->set_src = set_src;
return slot;
@@ -7838,7 +7838,7 @@ set_slot_part (dataflow_set *set, rtx loc, variable **slot,
deleting this one. */
if (node->init > initialized)
initialized = node->init;
- if (node->set_src != NULL && set_src == NULL)
+ if (node->set_src != NULL && set_src == NULL_RTX)
set_src = node->set_src;
if (var->var_part[pos].cur_loc == node->loc)
var->var_part[pos].cur_loc = NULL;
@@ -8348,10 +8348,10 @@ vt_expand_var_loc_chain (variable *var, bitmap regs, void *data,
class expand_loc_callback_data *elcd
= (class expand_loc_callback_data *) data;
location_chain *loc, *next;
- rtx result = NULL;
+ rtx result = NULL_RTX;
int first_child, result_first_child, last_child;
bool pending_recursion;
- rtx loc_from = NULL;
+ rtx loc_from = NULL_RTX;
struct elt_loc_list *cloc = NULL;
expand_depth depth = { 0, 0 }, saved_depth = elcd->depth;
int wanted_entryvals, found_entryvals = 0;
@@ -8424,12 +8424,12 @@ vt_expand_var_loc_chain (variable *var, bitmap regs, void *data,
found_entryvals = depth.entryvals;
}
- result = NULL;
+ result = NULL_RTX;
}
/* Set it up in case we leave the loop. */
depth.complexity = depth.entryvals = 0;
- loc_from = NULL;
+ loc_from = NULL_RTX;
result_first_child = first_child;
}
@@ -8500,7 +8500,7 @@ vt_expand_loc_callback (rtx x, bitmap regs,
vt_expand_loc_callback, data);
if (!subreg)
- return NULL;
+ return NULL_RTX;
result = simplify_gen_subreg (GET_MODE (x), subreg,
GET_MODE (SUBREG_REG (x)),
@@ -8530,7 +8530,7 @@ vt_expand_loc_callback (rtx x, bitmap regs,
if (NO_LOC_P (x))
{
gcc_checking_assert (VALUE_RECURSED_INTO (x) || !dv_changed_p (dv));
- return NULL;
+ return NULL_RTX;
}
var = elcd->vars->find_with_hash (dv, dv_htab_hash (dv));
@@ -8799,7 +8799,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
&& (loc2 = vt_expand_loc (var->var_part[j].cur_loc, vars))
&& GET_CODE (loc[n_var_parts]) == GET_CODE (loc2))
{
- rtx new_loc = NULL;
+ rtx new_loc = NULL_RTX;
poly_int64 offset2;
if (REG_P (loc[n_var_parts])
@@ -8817,7 +8817,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
{
if (!REG_P (new_loc)
|| REGNO (new_loc) != REGNO (loc[n_var_parts]))
- new_loc = NULL;
+ new_loc = NULL_RTX;
else
REG_ATTRS (new_loc) = REG_ATTRS (loc[n_var_parts]);
}
@@ -9376,7 +9376,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else
{
dstv = uloc;
- srcv = NULL;
+ srcv = NULL_RTX;
}
if (GET_CODE (val) == CONCAT)
@@ -9420,7 +9420,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else
{
bool copied_p = VAL_EXPR_IS_COPIED (loc);
- rtx src = NULL, dst = uloc;
+ rtx src = NULL_RTX, dst = uloc;
enum var_init_status status = VAR_INIT_STATUS_INITIALIZED;
if (GET_CODE (uloc) == SET)
@@ -9468,7 +9468,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
case MO_SET:
{
rtx loc = mo->u.loc;
- rtx set_src = NULL;
+ rtx set_src = NULL_RTX;
if (GET_CODE (loc) == SET)
{
@@ -9492,7 +9492,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
{
rtx loc = mo->u.loc;
enum var_init_status src_status;
- rtx set_src = NULL;
+ rtx set_src = NULL_RTX;
if (GET_CODE (loc) == SET)
{
diff --git a/gcc/web.cc b/gcc/web.cc
index ef2d79e40e8..55a0287fa5f 100644
--- a/gcc/web.cc
+++ b/gcc/web.cc
@@ -187,7 +187,7 @@ union_defs (df_ref use, web_entry *def_entry,
(*fun) (use_entry + DF_REF_ID (use), use_entry + DF_REF_ID (eq_use));
}
else
- set = NULL;
+ set = NULL_RTX;
/* Union all occurrences of the same register in reg notes. */
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr
2023-05-26 8:31 ` Bernhard Reutner-Fischer
@ 2023-06-14 19:14 ` Bernhard Reutner-Fischer
2023-12-01 15:42 ` PING^3 " Bernhard Reutner-Fischer
0 siblings, 1 reply; 5+ messages in thread
From: Bernhard Reutner-Fischer @ 2023-06-14 19:14 UTC (permalink / raw)
To: Roger Sayle; +Cc: gcc-patches, 'Uros Bizjak', jeffreyalaw
plonk.
On 26 May 2023 10:31:51 CEST, Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
>On Thu, 25 May 2023 18:58:04 +0200
>Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
>
>> On Wed, 24 May 2023 18:54:06 +0100
>> "Roger Sayle" <roger@nextmovesoftware.com> wrote:
>>
>> > My understanding is that GCC's preferred null value for rtx is NULL_RTX
>> > (and for tree is NULL_TREE), and by being typed allows strict type checking,
>> > and use with function polymorphism and template instantiation.
>> > C++'s nullptr is preferred over NULL and 0 for pointer types that don't
>> > have a defined null of the correct type.
>> >
>> > This minor clean-up uses NULL_RTX consistently in i386-expand.cc.
>>
>> Oh. Well, i can't resist cleanups :)
>
>> (and handle nullptr too, and the same game for tree)
>
>so like the attached. And
>sed -e 's/RTX/TREE/g' -e 's/rtx/tree/g' \
> < ~/coccinelle/gcc-rtx-null.0.cocci \
> > ~/coccinelle/gcc-tree-null.0.cocci
>
>I do not know if we want to shorten explicit NULL comparisons.
> foo == NULL => !foo and foo != NULL => foo
>Left them alone in the form they were written.
>
>See the attached result of the rtx hunks, someone would have to build
I've bootstrapped and regtested the hunks for rtx as cited up-thread without regressions (as expected).
I know everybody is busy, but I'd like to know if I should swap these out completely, or postpone this until start of stage3 or next stage 1 or something.
I can easily keep these local to my personal pre-configure stage for my own amusement.
thanks,
>it and hack git-commit-mklog.py --changelog 'Use NULL_RTX.'
>to print("{}.".format(random.choice(['Ditto', 'Same', 'Likewise']))) ;)
>
>>
>> Just a thought..
>
>cheers,
^ permalink raw reply [flat|nested] 5+ messages in thread
* PING^3 Re: [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr
2023-06-14 19:14 ` Bernhard Reutner-Fischer
@ 2023-12-01 15:42 ` Bernhard Reutner-Fischer
0 siblings, 0 replies; 5+ messages in thread
From: Bernhard Reutner-Fischer @ 2023-12-01 15:42 UTC (permalink / raw)
To: jeffreyalaw; +Cc: rep.dot.nop, Roger Sayle, gcc-patches, 'Uros Bizjak'
On Wed, 14 Jun 2023 21:14:02 +0200
Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
> plonk.
ping^3
patch at
https://inbox.sourceware.org/gcc-patches/20230526103151.3a7f65d0@nbbrfq.loc/
I would regenerate it for rtx and/or tree, though, whatever you deem
desirable?
thanks
>
> On 26 May 2023 10:31:51 CEST, Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
> >On Thu, 25 May 2023 18:58:04 +0200
> >Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> wrote:
> >
> >> On Wed, 24 May 2023 18:54:06 +0100
> >> "Roger Sayle" <roger@nextmovesoftware.com> wrote:
> >>
> >> > My understanding is that GCC's preferred null value for rtx is NULL_RTX
> >> > (and for tree is NULL_TREE), and by being typed allows strict type checking,
> >> > and use with function polymorphism and template instantiation.
> >> > C++'s nullptr is preferred over NULL and 0 for pointer types that don't
> >> > have a defined null of the correct type.
> >> >
> >> > This minor clean-up uses NULL_RTX consistently in i386-expand.cc.
> >>
> >> Oh. Well, i can't resist cleanups :)
> >
> >> (and handle nullptr too, and the same game for tree)
> >
> > so like the attached. And
> > sed -e 's/RTX/TREE/g' -e 's/rtx/tree/g' \
> > < ~/coccinelle/gcc-rtx-null.0.cocci \
> > > ~/coccinelle/gcc-tree-null.0.cocci
> >
> > I do not know if we want to shorten explicit NULL comparisons.
> > foo == NULL => !foo and foo != NULL => foo
> > Left them alone in the form they were written.
> >
> > See the attached result of the rtx hunks, someone would have to build
>
> I've bootstrapped and regtested the hunks for rtx as cited up-thread without regressions (as expected).
>
> I know everybody is busy, but I'd like to know if I should swap these out completely,
> or postpone this until start of stage3 or next stage 1 or something.
> I can easily keep these local to my personal pre-configure stage for my own amusement.
>
> thanks,
>
> >it and hack git-commit-mklog.py --changelog 'Use NULL_RTX.'
> >to print("{}.".format(random.choice(['Ditto', 'Same', 'Likewise']))) ;)
> >
> >>
> >> Just a thought..
> >
> >cheers,
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-12-01 15:42 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-24 17:54 [i386 PATCH] A minor code clean-up: Use NULL_RTX instead of nullptr Roger Sayle
2023-05-25 16:58 ` Bernhard Reutner-Fischer
2023-05-26 8:31 ` Bernhard Reutner-Fischer
2023-06-14 19:14 ` Bernhard Reutner-Fischer
2023-12-01 15:42 ` PING^3 " Bernhard Reutner-Fischer
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