RISC-V: Support XTheadVector extensions

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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90% theadvector extension reusing current RVV 1.0 instructions patterns:
Just change ASM, For example:

@@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh<v_su><mode>_scalar"
 	     (match_operand:VFULLI_D 3 "register_operand"  "vr,vr, vr, vr")] VMULH)
 	  (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vmulh<v_su>.vx\t%0,%3,%z4%p1"
+  "%^vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])
+  if (letter == '^')
+    {
+      if (TARGET_XTHEADVECTOR)
+	fputs ("th.", file);
+      return;
+    }

For almost all patterns, you just simply append "th." in the ASM prefix.
like change "vmulh.vv" -> "th.vmulh.vv"

Almost all theadvector instructions are not new features,  all same as RVV1.0.
Why do you invent the such ISA doesn't include any features that RVV1.0 doesn't satisfy ?

I am not explicitly object this patch. But I should know the reason.

Btw, stage 1 will close soon.  So I will review this patch on GCC-15 as long as all other RISC-V maintainers agree.




juzhe.zhong@rivai.ai