From: Jeff Law <jeffreyalaw@gmail.com>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions
Date: Tue, 22 Nov 2022 08:20:15 -0700 [thread overview]
Message-ID: <113a2b0a-8b8a-3d6c-60ec-8d57cf7350f4@gmail.com> (raw)
In-Reply-To: <CA+yXCZCd74WgLn16KQgx2hiWBZS5x3mDoBywqDb-KTaWLHPEeg@mail.gmail.com>
On 11/20/22 18:36, Kito Cheng wrote:
>> So the idea here is just to define the extension so that it gets defined
>> in the ISA strings and passed through to the assembler, right?
> That will also define arch test marco:
>
> https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro
Sorry I should have been clearer and included the test macro(s) as well.
So a better summary would be that while it doesn't change the codegen
behavior in the compiler, it does provide the mechanisms to pass along
isa strings to other tools such as the assembler and signal via the test
macros that this extension is available.
If so I think that it meets Andrew's requirements and at least some of
those issues raised by Jim. But I'm not sure it can address your
concern WRT consistency. In fact, I don't really see a way to address
that concern with option #2 which Andrew seems to think is the only
reasonable path forward from an RVI standpoint.
I'm at a loss for next steps, particularly as the newbie in this world.
jeff
next prev parent reply other threads:[~2022-11-22 15:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 3:00 Palmer Dabbelt
2022-11-18 2:14 ` Christoph Müllner
2022-11-18 4:29 ` Palmer Dabbelt
2022-11-20 16:19 ` Jeff Law
2022-11-21 1:36 ` Kito Cheng
2022-11-22 15:20 ` Jeff Law [this message]
2022-11-22 15:29 ` Palmer Dabbelt
2022-11-22 21:50 ` Jeff Law
2022-11-22 22:00 ` Palmer Dabbelt
2024-01-19 8:01 ` Kito Cheng
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