From: Peter Bergner <bergner@linux.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: "Kewen.Lin" <linkw@linux.ibm.com>,
GCC Patches <gcc-patches@gcc.gnu.org>,
David Edelsohn <dje.gcc@gmail.com>
Subject: Re: [PATCH] rs6000/test: Fix bswap64-4.c with has_arch_ppc64 [PR106680]
Date: Wed, 31 Aug 2022 12:00:14 -0500 [thread overview]
Message-ID: <16dc8d80-44d5-b739-b4a8-d02a01943d49@linux.ibm.com> (raw)
In-Reply-To: <20220831160529.GR25951@gate.crashing.org>
On 8/31/22 11:05 AM, Segher Boessenkool wrote:
> On Wed, Aug 31, 2022 at 10:48:26AM -0500, Peter Bergner wrote:
>> Ditto for -msoft-float better disable any -maltivec and -mvsx, etc.
>
> Oh? Why should it disable -maltivec? -mvsx makes a little sense on
> one hand, but totally none on the other either.
VSX has to be disabled, since VSX replies on the FP registers existing.
As for Altivec, I'm pretty sure there are some inherent dependencies
there, probably both in hardware and our GCC backend implementation.
I could be wrong, but my guess is things will fall over the ground
if as allow -maltivec along with -msoft-float. Does the linux kernel
only build with -msoft-float assuming it disables altivec and vsx?
Or does it explicitly always also add -mno-altivec?
> As far as I always knew it does *not* override it, so this seems like
> an accident to me, not detected before because everyone always types
> -m32 -mpowerpc64 (I know I do, anyway).
>
> I think we should just fix this and see what breaks, if anything?
So in linux*.h, we have the following which came from a 2004 commit from Alan:
linux64.h:#define OS_MISSING_POWERPC64 !TARGET_64BIT
...and in rs6000.cc:rs6000_option_override_internal(), the following hunk is
basically from:
+2003-12-18 Geoffrey Keating <geoffk@apple.com>
+
+ * config/rs6000/aix.h (OS_MISSING_POWERPC64): Define.
+ (OS_MISSING_ALTIVEC): Define.
+ * config/rs6000/darwin.h (ASM_SPEC): Be generous about supplying
+ -force_cpusubtype_ALL.
+ * config/rs6000/rs6000.c (rs6000_override_options): Rearrange
+ CPU information table; now always set all CPU-specific values.
+ Also, use Altivec and powerpc64 when chip and OS supports them.
/* Some OSs don't support saving the high part of 64-bit registers on context
switch. Other OSs don't support saving Altivec registers. On those OSs,
we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
if the user wants either, the user must explicitly specify them and we
won't interfere with the user's specification. */
set_masks = POWERPC_MASKS;
#ifdef OS_MISSING_POWERPC64
if (OS_MISSING_POWERPC64)
set_masks &= ~OPTION_MASK_POWERPC64;
#endif
#ifdef OS_MISSING_ALTIVEC
if (OS_MISSING_ALTIVEC)
set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
| OTHER_VSX_VECTOR_MASKS);
#endif
...so I think there was no real reason, other than old 64-bit linux kernels didn't
save the upper register state in 32-bit mode binaries. I believe that was "fixed"
a long time ago, so I agree we should just "fix" it and see what happens.
In this case, I think the fix is probably just to change the linux64.h define
to be "0" rather than "!TARGET_64".
Peter
next prev parent reply other threads:[~2022-08-31 17:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 9:33 Kewen.Lin
2022-08-31 14:13 ` Peter Bergner
2022-09-01 8:57 ` Kewen.Lin
2022-09-01 14:57 ` Segher Boessenkool
2022-09-02 0:50 ` Kewen.Lin
2022-09-02 17:36 ` Segher Boessenkool
2022-09-05 2:25 ` Kewen.Lin
2022-08-31 15:24 ` Segher Boessenkool
2022-08-31 15:48 ` Peter Bergner
2022-08-31 16:05 ` Segher Boessenkool
2022-08-31 17:00 ` Peter Bergner [this message]
2022-08-31 19:28 ` Segher Boessenkool
2022-08-31 19:53 ` Peter Bergner
2022-08-31 21:07 ` Segher Boessenkool
2022-08-31 21:38 ` Peter Bergner
2022-08-31 21:49 ` Segher Boessenkool
2022-08-31 22:17 ` Peter Bergner
2022-09-01 9:05 ` Kewen.Lin
2022-09-01 15:04 ` Segher Boessenkool
2022-09-02 0:51 ` Kewen.Lin
2022-09-02 17:44 ` Segher Boessenkool
2022-09-05 2:35 ` Kewen.Lin
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