From: shiyulong@iscas.ac.cn
To: gcc-patches@gcc.gnu.org
Cc: andrew@sifive.com, palmer@dabbelt.com, kito.cheng@gmail.com,
jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn,
jiawei@iscas.ac.cn, shihua@iscas.ac.cn,
yulong <shiyulong@iscas.ac.cn>
Subject: [PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases
Date: Tue, 10 May 2022 11:25:26 +0800 [thread overview]
Message-ID: <20220510032526.11560-4-shiyulong@iscas.ac.cn> (raw)
In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn>
From: yulong <shiyulong@iscas.ac.cn>
This commit adds testcases about CMO instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c: New test.
* gcc.target/riscv/cmo-zicbom-2.c: New test.
* gcc.target/riscv/cmo-zicbop-1.c: New test.
* gcc.target/riscv/cmo-zicbop-2.c: New test.
* gcc.target/riscv/cmo-zicboz-1.c: New test.
* gcc.target/riscv/cmo-zicboz-2.c: New test.
---
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++++++
gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++++++
6 files changed, 106 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
new file mode 100644
index 00000000000..e2ba2183511
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+ return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+ return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
new file mode 100644
index 00000000000..a605e8b1bdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+ return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+ return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
new file mode 100644
index 00000000000..c5d78c1763d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+ return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
new file mode 100644
index 00000000000..6576365b39c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv32-*-*}}} */
+/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+ return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
new file mode 100644
index 00000000000..96c1674ef2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicboz_cbo_zero();
+}
+
+/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
new file mode 100644
index 00000000000..9d99839b1e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicboz -mabi=ilp32" } */
+
+int foo1()
+{
+ return __builtin_riscv_zicboz_cbo_zero();
+}
+
+/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
--
2.17.1
next prev parent reply other threads:[~2022-05-10 3:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 3:25 [PATCH V4 0/3] RISC-V:Add mininal support for Zicbo[mzp] shiyulong
2022-05-10 3:25 ` [PATCH V4 1/3] RISC-V: Add " shiyulong
2022-05-10 3:25 ` [PATCH V4 2/3] RISC-V:Cache Management Operation instructions shiyulong
2022-05-26 11:58 ` Simon Cook
2022-05-26 15:37 ` Kito Cheng
2022-05-10 3:25 ` shiyulong [this message]
2022-05-24 13:02 ` [PATCH V4 0/3] RISC-V:Add mininal support for Zicbo[mzp] Kito Cheng
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