From: shiyulong@iscas.ac.cn
To: gcc-patches@gcc.gnu.org
Cc: andrew@sifive.com, palmer@dabbelt.com, kito.cheng@gmail.com,
jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn,
jiawei@iscas.ac.cn, shihua@iscas.ac.cn,
yulong <shiyulong@iscas.ac.cn>
Subject: [PATCH V4 1/3] RISC-V: Add mininal support for Zicbo[mzp]
Date: Tue, 10 May 2022 11:25:24 +0800 [thread overview]
Message-ID: <20220510032526.11560-2-shiyulong@iscas.ac.cn> (raw)
In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn>
From: yulong <shiyulong@iscas.ac.cn>
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
(MASK_ZICBOP): New.
(TARGET_ZICBOZ): New.
(TARGET_ZICBOM): New.
(TARGET_ZICBOP): New.
* config/riscv/riscv.opt: New.
---
gcc/common/config/riscv/riscv-common.cc | 8 ++++++++
gcc/config/riscv/riscv-opts.h | 8 ++++++++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 19 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..bf7a7caabef 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
{"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT},
+ {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
+ {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
+ {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
+
{"zve32x", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve32f", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve64x", &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..1e153b3a6e7 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -145,6 +145,14 @@ enum stack_protector_guard {
#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
+#define MASK_ZICBOZ (1 << 0)
+#define MASK_ZICBOM (1 << 1)
+#define MASK_ZICBOP (1 << 2)
+
+#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
+#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
+#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
+
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN. */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 492aad12324..d1b3c1840a6 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,6 +209,9 @@ int riscv_vector_elen_flags
TargetVariable
int riscv_zvl_flags
+TargetVariable
+int riscv_zicmo_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
--
2.17.1
next prev parent reply other threads:[~2022-05-10 3:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 3:25 [PATCH V4 0/3] RISC-V:Add " shiyulong
2022-05-10 3:25 ` shiyulong [this message]
2022-05-10 3:25 ` [PATCH V4 2/3] RISC-V:Cache Management Operation instructions shiyulong
2022-05-26 11:58 ` Simon Cook
2022-05-26 15:37 ` Kito Cheng
2022-05-10 3:25 ` [PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases shiyulong
2022-05-24 13:02 ` [PATCH V4 0/3] RISC-V:Add mininal support for Zicbo[mzp] Kito Cheng
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