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From: "Torbjörn SVENSSON" <torbjorn.svensson@foss.st.com>
To: <gcc-patches@gcc.gnu.org>
Cc: yvan.roux@foss.st.com, ro@CeBiTec.Uni-Bielefeld.DE,
	mikestump@comcast.net,
	"Torbjörn SVENSSON" <torbjorn.svensson@foss.st.com>
Subject: [PATCH] testsuite: Sanitize fails for SP FPU on Arm
Date: Thu, 22 Sep 2022 18:40:58 +0200	[thread overview]
Message-ID: <20220922164057.4107373-1-torbjorn.svensson@foss.st.com> (raw)

This patch stops reporting fails for Arm targets with single
precision floating point unit for types wider than 32 bits (the width
of float on arm-none-eabi).

As reported in PR102017, fenv is reported as supported in recent
versions of newlib. At the same time, for some Arm targets, the
implementation in libgcc does not support exceptions and thus, the
test fails with a call to abort().

gcc/testsuite/ChangeLog:

	* gcc.dg/c2x-float-7.c: Invert the exception check for Arm
	targets with SP FPU.
	* gcc.dg/pr95115.c: Likewise.
	* gcc.dg/torture/float32x-nan-floath.c: Likewise.
	* gcc.dg/torture/float32x-nan.c: Likewise.
	* gcc.dg/torture/float64-nan-floath.c: Likewise.
	* gcc.dg/torture/float64-nan.c: Likewise.
	* gcc.dg/torture/inf-compare-1.c: Likewise.
	* gcc.dg/torture/inf-compare-2.c: Likewise.
	* gcc.dg/torture/inf-compare-3.c: Likewise.
	* gcc.dg/torture/inf-compare-4.c: Likewise.

Co-Authored-By: Yvan ROUX  <yvan.roux@foss.st.com>
Signed-off-by: Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
---
 gcc/testsuite/gcc.dg/c2x-float-7.c               | 10 ++++++++++
 gcc/testsuite/gcc.dg/pr95115.c                   |  5 +++++
 gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h |  5 +++++
 gcc/testsuite/gcc.dg/torture/floatn-nan.h        | 10 ++++++++++
 gcc/testsuite/gcc.dg/torture/inf-compare-1.c     |  5 +++++
 gcc/testsuite/gcc.dg/torture/inf-compare-2.c     |  5 +++++
 gcc/testsuite/gcc.dg/torture/inf-compare-3.c     |  5 +++++
 gcc/testsuite/gcc.dg/torture/inf-compare-4.c     |  5 +++++
 8 files changed, 50 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/c2x-float-7.c b/gcc/testsuite/gcc.dg/c2x-float-7.c
index 0c90ff24165..c699e94aff8 100644
--- a/gcc/testsuite/gcc.dg/c2x-float-7.c
+++ b/gcc/testsuite/gcc.dg/c2x-float-7.c
@@ -39,11 +39,21 @@ main (void)
     abort ();
   feclearexcept (FE_ALL_EXCEPT);
   d += d;
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (fetestexcept (FE_INVALID))
+#else
   if (!fetestexcept (FE_INVALID))
+#endif
     abort ();
   feclearexcept (FE_ALL_EXCEPT);
   ld += ld;
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (fetestexcept (FE_INVALID))
+#else
   if (!fetestexcept (FE_INVALID))
+#endif
     abort ();
   exit (0);
 }
diff --git a/gcc/testsuite/gcc.dg/pr95115.c b/gcc/testsuite/gcc.dg/pr95115.c
index 46a95dfb698..15bc6854819 100644
--- a/gcc/testsuite/gcc.dg/pr95115.c
+++ b/gcc/testsuite/gcc.dg/pr95115.c
@@ -19,7 +19,12 @@ main (void)
   double r = x ();
   if (!__builtin_isnan (r))
 	abort ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (fetestexcept (FE_INVALID))
+#else
   if (!fetestexcept (FE_INVALID))
+#endif
 	abort ();
   exit (0);
 }
diff --git a/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h b/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h
index 9892fd0cf63..5c9f28d4fdc 100644
--- a/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h
+++ b/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h
@@ -30,7 +30,12 @@ main (void)
 {
   volatile TYPE r;
   r = nans_cst + nans_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (fetestexcept (FE_INVALID))
+#else
   if (!fetestexcept (FE_INVALID))
+#endif
     abort ();
   exit (0);
 }
diff --git a/gcc/testsuite/gcc.dg/torture/floatn-nan.h b/gcc/testsuite/gcc.dg/torture/floatn-nan.h
index 89d2e2eec34..0abb0668677 100644
--- a/gcc/testsuite/gcc.dg/torture/floatn-nan.h
+++ b/gcc/testsuite/gcc.dg/torture/floatn-nan.h
@@ -30,10 +30,20 @@ main (void)
 {
   volatile TYPE r;
   r = nan_cst + nan_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (!fetestexcept (FE_INVALID))
+#else
   if (fetestexcept (FE_INVALID))
+#endif
     abort ();
   r = nans_cst + nans_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (fetestexcept (FE_INVALID))
+#else
   if (!fetestexcept (FE_INVALID))
+#endif
     abort ();
   exit (0);
 }
diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-1.c b/gcc/testsuite/gcc.dg/torture/inf-compare-1.c
index 70f255e680a..df0e61d9f89 100644
--- a/gcc/testsuite/gcc.dg/torture/inf-compare-1.c
+++ b/gcc/testsuite/gcc.dg/torture/inf-compare-1.c
@@ -16,6 +16,11 @@ int
 main (void)
 {
   i = x > __builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (i != 0 || fetestexcept (FE_INVALID))
+#else
   if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
     abort ();
 }
diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-2.c b/gcc/testsuite/gcc.dg/torture/inf-compare-2.c
index 011f992d5a0..dcb43ccc444 100644
--- a/gcc/testsuite/gcc.dg/torture/inf-compare-2.c
+++ b/gcc/testsuite/gcc.dg/torture/inf-compare-2.c
@@ -16,6 +16,11 @@ int
 main (void)
 {
   i = x < -__builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (i != 0 || fetestexcept (FE_INVALID))
+#else
   if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
     abort ();
 }
diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-3.c b/gcc/testsuite/gcc.dg/torture/inf-compare-3.c
index de5c478a8d8..1cd4d3e8199 100644
--- a/gcc/testsuite/gcc.dg/torture/inf-compare-3.c
+++ b/gcc/testsuite/gcc.dg/torture/inf-compare-3.c
@@ -16,6 +16,11 @@ int
 main (void)
 {
   i = x <= __builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (i != 0 || fetestexcept (FE_INVALID))
+#else
   if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
     abort ();
 }
diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-4.c b/gcc/testsuite/gcc.dg/torture/inf-compare-4.c
index 685562d3a40..0cd27076079 100644
--- a/gcc/testsuite/gcc.dg/torture/inf-compare-4.c
+++ b/gcc/testsuite/gcc.dg/torture/inf-compare-4.c
@@ -16,6 +16,11 @@ int
 main (void)
 {
   i = x >= -__builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+  /* Arm with SP FPU does not support exceptions (see pr102017).  */
+  if (i != 0 || fetestexcept (FE_INVALID))
+#else
   if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
     abort ();
 }
-- 
2.25.1


             reply	other threads:[~2022-09-22 16:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22 16:40 Torbjörn SVENSSON [this message]
2022-09-22 22:42 ` Joseph Myers
2022-09-23 10:03   ` Torbjorn SVENSSON

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