From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Remove unused TI/TF vector modes.
Date: Mon, 24 Oct 2022 10:05:24 +0800 [thread overview]
Message-ID: <20221024020524.27704-1-juzhe.zhong@rivai.ai> (raw)
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes.
---
gcc/config/riscv/riscv-vector-switch.def | 4 ----
1 file changed, 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index cacfccb6d29..ee8ebd5f1cc 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64)
ENTRY (VNx2DF, TARGET_VECTOR_FP64)
ENTRY (VNx1DF, TARGET_VECTOR_FP64)
-/* SEW = 128. Disable all of them. */
-ENTRY (VNx2TI, false)
-ENTRY (VNx2TF, false)
-
#undef TARGET_VECTOR_FP32
#undef TARGET_VECTOR_FP64
#undef ENTRY
--
2.36.1
next reply other threads:[~2022-10-24 2:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 2:05 juzhe.zhong [this message]
2022-10-24 2:21 ` Kito Cheng
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