[PATCH] RISC-V: split to allow formation of sh[123]add before divw

[Philipp Tomsich <philipp.tomsich@vrull.eu>]

When using strength-reduction, we will reduce a multiplication to a
sequence of shifts and adds.  If this is performed with 32-bit types
and followed by a division, the lack of w-form sh[123]add will make
combination impossible and lead to a slli + addw being generated.

Split the sequence with the knowledge that a w-form div will perform
implicit sign-extensions.

gcc/ChangeLog:

        * config/riscv/bitmanip.md: Add a define_split to optimize
          slliw + addiw + divw into sh[123]add + divw.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zba-shNadd-05.c: New test.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

---

 gcc/config/riscv/bitmanip.md                   | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c | 11 +++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 30dabdf8ddc..726a07b0d90 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -39,6 +39,23 @@
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
 
+; When using strength-reduction, we will reduce a multiplication to a
+; sequence of shifts and adds.  If this is performed with 32-bit types
+; and followed by a division, the lack of w-form sh[123]add will make
+; combination impossible and lead to a slli + addw being generated.
+; Split the sequence with the knowledge that a w-form div will perform
+; implicit sign-extensions.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(sign_extend:DI (div:SI (plus:SI (subreg:SI (ashift:DI (match_operand:DI 1 "register_operand")
+							       (match_operand:QI 2 "imm123_operand")) 0)
+						    (subreg:SI (match_operand:DI 3 "register_operand") 0))
+		(subreg:SI (match_operand:DI 4 "register_operand") 0))))
+   (clobber (match_operand:DI 5 "register_operand"))]
+  "TARGET_64BIT && TARGET_ZBA"
+   [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+    (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 4) 0))))])
+
 (define_insn "*shNadduw"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c
new file mode 100644
index 00000000000..271c3a8c0ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+
+long long f(int a, int b)
+{
+  return (a * 3) / b;
+}
+
+/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
+/* { dg-final { scan-assembler-times "divw\t" 1 } } */
-- 
2.34.1