Re: [PATCH] RISC-V: split to allow formation of sh[123]add before divw

[Jeff Law <jeffreyalaw@gmail.com>]

On 11/8/22 12:56, Philipp Tomsich wrote:
> When using strength-reduction, we will reduce a multiplication to a
> sequence of shifts and adds.  If this is performed with 32-bit types
> and followed by a division, the lack of w-form sh[123]add will make
> combination impossible and lead to a slli + addw being generated.
>
> Split the sequence with the knowledge that a w-form div will perform
> implicit sign-extensions.
>
> gcc/ChangeLog:
>
>          * config/riscv/bitmanip.md: Add a define_split to optimize
>            slliw + addiw + divw into sh[123]add + divw.
>
> gcc/testsuite/ChangeLog:
>
>          * gcc.target/riscv/zba-shNadd-05.c: New test.

OK.  I won't complain about the subregs on this one :-)


jeff