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From: Jeff Law <>
To: Philipp Tomsich <>,
Cc: Kito Cheng <>,
	Vineet Gupta <>,
	Palmer Dabbelt <>,
	Christoph Muellner <>,
	Jeff Law <>
Subject: Re: [PATCH] RISC-V: split to allow formation of sh[123]add before divw
Date: Fri, 18 Nov 2022 12:37:45 -0700	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 11/8/22 12:56, Philipp Tomsich wrote:
> When using strength-reduction, we will reduce a multiplication to a
> sequence of shifts and adds.  If this is performed with 32-bit types
> and followed by a division, the lack of w-form sh[123]add will make
> combination impossible and lead to a slli + addw being generated.
> Split the sequence with the knowledge that a w-form div will perform
> implicit sign-extensions.
> gcc/ChangeLog:
>          * config/riscv/ Add a define_split to optimize
>            slliw + addiw + divw into sh[123]add + divw.
> gcc/testsuite/ChangeLog:
>          * New test.

OK.  I won't complain about the subregs on this one :-)


  reply	other threads:[~2022-11-18 19:37 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-08 19:56 Philipp Tomsich
2022-11-18 19:37 ` Jeff Law [this message]
2022-11-18 19:56   ` Philipp Tomsich

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