From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@gmail.com>,
Vineet Gupta <vineetg@rivosinc.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Jeff Law <jlaw@ventanamicro.com>
Subject: Re: [PATCH] RISC-V: split to allow formation of sh[123]add before divw
Date: Fri, 18 Nov 2022 20:56:13 +0100 [thread overview]
Message-ID: <CAAeLtUCZv1rCXaNoDQC8+gCk0hYRb3rjuks9fCSjSL+Bx9_0YQ@mail.gmail.com> (raw)
In-Reply-To: <a3d1e1d9-0965-5338-26da-274c01c3d1b0@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 881 bytes --]
Applied to master. Thanks!
--Philipp.
On Fri, 18 Nov 2022 at 20:37, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
> On 11/8/22 12:56, Philipp Tomsich wrote:
> > When using strength-reduction, we will reduce a multiplication to a
> > sequence of shifts and adds. If this is performed with 32-bit types
> > and followed by a division, the lack of w-form sh[123]add will make
> > combination impossible and lead to a slli + addw being generated.
> >
> > Split the sequence with the knowledge that a w-form div will perform
> > implicit sign-extensions.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/bitmanip.md: Add a define_split to optimize
> > slliw + addiw + divw into sh[123]add + divw.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/zba-shNadd-05.c: New test.
>
> OK. I won't complain about the subregs on this one :-)
>
>
> jeff
>
>
>
prev parent reply other threads:[~2022-11-18 19:56 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 19:56 Philipp Tomsich
2022-11-18 19:37 ` Jeff Law
2022-11-18 19:56 ` Philipp Tomsich [this message]
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